| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460D |
| Non-Confidential | ID092411 |
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| Home > Level One Memory System > About the caches > Cache maintenance operations |
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All cache maintenance operations are done through the system control coprocessor, CP15. The system control coprocessor operations supported for the data cache are:
Invalidate all
Invalidate by address (MVA)
Invalidate by Set/Way combination
Clean by address (MVA)
Clean by Set/Way combination
Clean and Invalidate by address (MVA)
Clean and Invalidate by Set/Way combination
Data Memory Barrier (DMB) and Data Synchronization Barrier (DSB) operations.
The system control coprocessor operations supported for the instruction cache are:
Invalidate all
Invalidate by address.
For more information on cache operations, see Cache operations.
| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460D |
| Non-Confidential | ID092411 |
| PDF version | |
| Home > Level One Memory System > About the caches > Cache maintenance operations |