Cortex™-R5 Technical Reference Manual

Revision: r1p2


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Trace macrocell
1.2.3. Advanced Microcontroller Bus Architecture
1.2.4. Debug architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.5.1. CPU configurations
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.8. Changes from previous version
2. Functional Description
2.1. About the functions
2.1.1. Data Processing Unit
2.1.2. Load/Store Unit
2.1.3. PreFetch Unit
2.1.4. L1 memory system
2.1.5. L2 AXI interfaces
2.1.6. Dual-redundant core
2.1.7. Split/lock
2.1.8. Hard error features
2.1.9. Debug
2.1.10. System control coprocessor
2.1.11. Interrupt handling
2.1.12. Power management
2.2. Interfaces
2.2.1. AXI master interface
2.2.2. Peripheral interfaces
2.2.3. AXI slave interface
2.2.4. TCM interfaces
2.2.5. ACP interface
2.2.6. Interrupt and VIC interface
2.2.7. Configuration interface
2.2.8. Interrupt and event outputs
2.2.9. APB Debug interface
2.2.10. ETM interface
2.2.11. Test interface
2.3. Clocking and resets
2.3.1. Resets
2.3.2. Reset modes
2.3.3. Clocking
2.4. Operation
2.4.1. Initialization
3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution
3.2.1. Instruction set states
3.2.2. Modes of operation
3.3. Memory model
3.3.1. Byte-invariant big-endian format
3.3.2. Little-endian format
3.4. Coherency
3.5. Data structures
3.6. Registers
3.6.1. The register set
3.7. Program status registers
3.7.1. The N, Z, C, and V bits
3.7.2. The Q bit
3.7.3. The IT bits
3.7.4. The J bit
3.7.5. The DNM bits
3.7.6. The GE bits
3.7.7. The E bit
3.7.8. The A bit
3.7.9. The I and F bits
3.7.10. The T bit
3.7.11. The M bits
3.7.12. Modification of PSR bits by MSR instructions
3.8. Exceptions
3.8.1. Exception entry and exit summary
3.8.2. Reset
3.8.3. Interrupts
3.8.4. Aborts
3.8.5. Supervisor call instruction
3.8.6. Undefined Instruction
3.8.7. Breakpoint instruction
3.8.8. Exception vectors
3.9. Acceleration of execution environments
3.10. Unaligned and mixed-endian data access support
3.11. Big-endian instruction support
4. System Control
4.1. About system control
4.1.1. System control and configuration
4.1.2. MPU control and configuration
4.1.3. Cache control and configuration
4.1.4. Interface control and configuration
4.1.5. System performance monitor
4.1.6. System validation
4.2. Register summary
4.3. Register descriptions
4.3.1. Register allocation
4.3.2. c0, Main ID Register
4.3.3. c0, Cache Type Register
4.3.4. c0, TCM Type Register
4.3.5. c0, MPU Type Register
4.3.6. c0, Multiprocessor Affinity Register
4.3.7. The Processor Feature Registers
4.3.8. c0, Debug Feature Register 0
4.3.9. c0, Auxiliary Feature Register 0
4.3.10. Memory Model Feature Registers
4.3.11. Instruction Set Attributes Registers
4.3.12. c0, Cache Size ID Register
4.3.13. c0, Cache Level ID Register
4.3.14. c0, Auxiliary ID Register
4.3.15. c0, Cache Size Selection Register
4.3.16. c1, System Control Register
4.3.17. c1, Auxiliary Control Register
4.3.18. c15, Secondary Auxiliary Control Register
4.3.19. c1, Coprocessor Access Control Register
4.3.20. Fault Status and Address Registers
4.3.21. c6, MPU memory region programming registers
4.3.22. Cache operations
4.3.23. c9, BTCM Region Register
4.3.24. c9, ATCM Region Register
4.3.25. c9, TCM Selection Register
4.3.26. c11, Slave Port Control Register
4.3.27. c13, FCSE PID Register
4.3.28. c13, Context ID Register
4.3.29. c13, Thread and Process ID Registers
4.3.30. Validation Registers
4.3.31. Correctable Fault Location Register
4.3.32. Build Options Registers
4.3.33. Pin Options Register
4.3.34. Peripheral interface region registers
5. Prefetch Unit
5.1. About the prefetch unit
5.2. Branch prediction
5.2.1. Branch predictor
5.2.2. Incorrect predictions and correction
5.3. Return stack
5.4. Controlling instruction prefetch and program flow prediction
6. Events and Performance Monitor
6.1. About the events
6.2. About the PMU
6.3. Performance monitoring registers
6.3.1. c9, Performance Monitor Control Register
6.3.2. c9, Count Enable Set Register
6.3.3. c9, Count Enable Clear Register
6.3.4. c9, Overflow Flag Status Register
6.3.5. c9, Software Increment Register
6.3.6. c9, Performance Counter Selection Register
6.3.7. c9, Cycle Count Register
6.3.8. c9, Event Type Selection Register
6.3.9. c9, Event Count Registers
6.3.10. c9, User Enable Register
6.3.11. c9, Interrupt Enable Set Register
6.3.12. c9, Interrupt Enable Clear Register
6.4. Event bus interface
6.4.1. Use of the event bus and counters
7. Memory Protection Unit
7.1. About the MPU
7.1.1. Memory regions
7.1.2. Overlapping regions
7.1.3. Background regions
7.1.4. TCM regions
7.1.5. Peripheral port regions
7.2. Memory types
7.2.1. Using memory types
7.3. Region attributes
7.4. MPU interaction with memory system
7.5. MPU faults
7.5.1. Background fault
7.5.2. Permission fault
7.5.3. Alignment fault
7.6. MPU software-accessible registers
8. Level One Memory System
8.1. About the L1 memory system
8.2. About the error detection and correction schemes
8.2.1. Parity
8.2.2. Error checking and correction
8.2.3. Read-Modify-Write
8.2.4. Hard errors
8.2.5. Error correction
8.3. Fault handling
8.3.1. Faults
8.3.2. Fault status information
8.3.3. Correctable Fault Location Register
8.3.4. Usage models
8.4. About the TCMs
8.4.1. TCM attributes and permissions
8.4.2. ATCM and BTCM configuration
8.4.3. TCM internal error detection and correction
8.4.4. TCM arbitration
8.4.5. TCM initialization
8.4.6. TCM port protocol
8.4.7. External TCM errors
8.4.8. AXI slave interfaces for TCMs
8.5. About the caches
8.5.1. Store buffer
8.5.2. Cache maintenance operations
8.5.3. Cache error detection and correction
8.5.4. Cache RAM organization
8.5.5. Cache interaction with memory system
8.6. Internal exclusive monitor
8.7. Memory types and L1 memory system behavior
8.8. Error detection events
8.8.1. TCM error events
8.8.2. Instruction-cache error events
8.8.3. Data-cache error events
8.8.4. Events and the CFLR
9. Level Two Interface
9.1. About the L2 interface
9.1.1. Bus ECC
9.2. AXI master interface
9.2.1. Identifiers for AXI bus accesses
9.2.2. Write response
9.2.3. Linefill buffers and the AXI master interface
9.2.4. Eviction buffer
9.2.5. AXI extensions
9.2.6. Memory system implications for AXI accesses
9.3. AXI master interface transfers
9.3.1. Restrictions on AXI transfers
9.3.2. Strongly Ordered and Device transactions
9.3.3. Linefills
9.3.4. Cache line write-back (eviction)
9.3.5. Non-cacheable reads
9.3.6. Non-cacheable or write-through writes
9.3.7. AXI transaction splitting
9.3.8. Normal write merging
9.4. AXI slave interface
9.4.1. AXI slave interface for cache RAMs
9.4.2. TCM ECC support
9.4.3. External TCM errors
9.4.4. Cache parity and ECC support
9.4.5. AXI slave control
9.4.6. AXI slave characteristics
9.5. Enabling or disabling AXI slave accesses
9.6. Accessing RAMs using the AXI slave interface
9.6.1. TCM RAM access
9.6.2. Cache RAM access
9.7. Peripheral interfaces
9.7.1. Peripheral interface configuration
9.7.2. Peripheral interface initialization
9.7.3. Peripheral interface attributes and permissions
9.7.4. Identifiers for AXI peripheral port accesses
9.7.5. Write response
9.7.6. Memory attributes
9.7.7. AXI peripheral port transfers
9.7.8. AHB peripheral port transfers
9.7.9. Semaphores
9.8. Accelerator Coherency Port interface
10. Power Control
10.1. About power control
10.2. Power management
10.2.1. Run mode
10.2.2. Standby mode
10.2.3. Dormant mode
10.2.4. Shutdown mode
10.2.5. Power Management Controller
10.2.6. Power mode interaction with ACP
10.2.7. Power mode interaction with debug
11. FPU Programmers Model
11.1. About the FPU programmers model
11.1.1. FPU functionality
11.1.2. About the VFPv3-D16 architecture
11.1.3. VFP instructions in a single-precision configuration
11.2. General-purpose registers
11.2.1. FPU views of the register bank
11.3. System registers
11.3.1. Floating-Point System ID Register
11.3.2. Floating-Point Status and Control Register
11.3.3. Floating-Point Exception Register, FPEXC
11.3.4. Media and VFP Feature Registers, MVFR0 and MVFR1
11.4. Modes of operation
11.4.1. Full-compliance mode
11.4.2. Flush-to-zero mode
11.4.3. Default NaN mode
11.5. Compliance with the IEEE 754 standard
11.5.1. Complete implementation of the IEEE 754 standard
11.5.2. IEEE 754 standard implementation choices
11.5.3. Exceptions
12. Debug
12.1. Debug systems
12.1.1. Debug host
12.1.2. Protocol converter
12.1.3. Debug target
12.2. About the debug unit
12.2.1. Halting debug-mode debugging
12.2.2. Monitor debug-mode debugging
12.2.3. Programming the debug unit
12.3. Debug register interface
12.3.1. Coprocessor registers
12.3.2. CP14 access permissions
12.3.3. Coprocessor registers summary
12.3.4. Memory-mapped registers
12.3.5. Memory addresses for breakpoints and watchpoints
12.3.6. Power domains
12.3.7. Effects of resets on debug registers
12.3.8. APB port access permissions
12.4. Debug register descriptions
12.4.1. CP14 c0, Debug ID Register
12.4.2. CP14 c0, Debug ROM Address Register
12.4.3. CP14 c0, Debug Self Address Offset Register
12.4.4. CP14 c1, Debug Status and Control Register
12.4.5. Data Transfer Register
12.4.6. Watchpoint Fault Address Register
12.4.7. Vector Catch Register
12.4.8. Debug State Cache Control Register
12.4.9. Instruction Transfer Register
12.4.10. Debug Run Control Register
12.4.11. Breakpoint Value Registers
12.4.12. Breakpoint Control Registers
12.4.13. Watchpoint Value Registers
12.4.14. Watchpoint Control Registers
12.4.15. Operating System Lock Status Register
12.4.16. Authentication Status Register
12.4.17. Device Power-down and Reset Control Register
12.4.18. Device Power-down and Reset Status Register
12.5. Management registers
12.5.1. Processor ID Registers
12.5.2. Claim Registers
12.5.3. Lock Access Register
12.5.4. Lock Status Register
12.5.5. Device Type Register
12.5.6. Debug Identification Registers
12.6. Debug events
12.6.1. Software debug event
12.6.2. Halting debug event
12.6.3. Behavior of the processor on debug events
12.6.4. Debug event priority
12.6.5. Watchpoint debug events
12.7. Debug exception
12.7.1. Effect of debug exceptions on CP15 registers and DBGWFAR
12.7.2. Avoiding unrecoverable states
12.8. Debug state
12.8.1. Entering debug state
12.8.2. Behavior of the PC and CPSR in debug state
12.8.3. Executing instructions in debug state
12.8.4. Writing to the CPSR in debug state
12.8.5. Privilege
12.8.6. Accessing registers and memory
12.8.7. Coprocessor instructions
12.8.8. Effect of debug state on non-invasive debug
12.8.9. Effects of debug events on processor registers
12.8.10. Exceptions in debug state
12.8.11. Leaving debug state
12.9. Cache debug
12.9.1. Cache pollution in debug state
12.9.2. Cache coherency in debug state
12.9.3. Cache usage profiling
12.10. External debug interface
12.10.1. APB signals
12.10.2. Miscellaneous debug signals
12.10.3. Authentication signals
12.11. Using the debug functionality
12.11.1. Debug communications channel
12.11.2. Programming breakpoints and watchpoints
12.11.3. Single-stepping
12.11.4. Debug state entry
12.11.5. Debug state exit
12.11.6. Accessing registers and memory in debug state
12.12. Debugging systems with energy management capabilities
12.12.1. Emulating power down
13. Integration Test Registers
13.1. About Integration Test Registers
13.2. Summary of the processor registers used for integration testing
13.3. Processor integration testing
13.3.1. Using the Integration Test Registers
13.3.2. Performing integration testing
13.3.3. DBGITETMIF Register (ETM interface)
13.3.4. DBGITMISCOUT Register (Miscellaneous Outputs)
13.3.5. DBGITMISCIN Register (Miscellaneous Inputs)
13.3.6. Integration Mode Control Register (DBGITCTRL)
A. Signal Descriptions
A.1. About the processor signal descriptions
A.2. Global signals
A.3. Configuration signals
A.4. Interrupt signals, including VIC interface signals
A.5. L2 interface signals
A.5.1. AXI master port
A.5.2. AXI master port error detection signals
A.5.3. AXI slave port
A.5.4. AXI slave port error detection signals
A.5.5. ACP slave port
A.5.6. ACP slave port error detection signals
A.5.7. ACP master port
A.5.8. ACP master port error detection signals
A.5.9. AXI peripheral port
A.5.10. AXI peripheral port error detection signals
A.5.11. AHB peripheral port
A.5.12. AHB peripheral port error detection signals
A.6. TCM interface signals
A.7. Redundant CPU signals
A.8. Debug interface signals
A.9. ETM interface signals
A.10. Test signals
A.11. MBIST signals
A.12. Validation signals
A.13. FPU signals
A.14. Split/Lock
A.15. Power modes
B. Cycle Timings and Interlock Behavior
B.1. About cycle timings and interlock behavior
B.1.1. Instruction execution overview
B.1.2. Conditional instructions
B.1.3. Flag-setting instructions
B.1.4. Definition of terms
B.1.5. Assembler language syntax
B.2. Register interlock examples
B.3. Data processing instructions
B.3.1. Cycle counts if destination is not PC
B.3.2. Cycle counts if destination is the PC
B.3.3. Example interlocks
B.4. QADD, QDADD, QSUB, and QDSUB instructions
B.5. Media data-processing
B.6. Sum of Absolute Differences (SAD)
B.6.1. Example interlocks
B.7. Multiplies
B.8. Divide
B.9. Branches
B.10. Processor state updating instructions
B.11. Single load and store instructions
B.11.1. Base register update
B.12. Load and Store Double instructions
B.13. Load and Store Multiple instructions
B.13.1. Load and Store Multiples, other than load multiples including the PC
B.13.2. Load Multiples, where the PC is in the register list
B.13.3. Example Interlocks
B.14. RFE and SRS instructions
B.15. Synchronization instructions
B.16. Coprocessor instructions
B.17. SVC, BKPT, Undefined, and Prefetch Aborted instructions
B.18. Miscellaneous instructions
B.19. Floating-point register transfer instructions
B.20. Floating-point load/store instructions
B.21. Floating-point single-precision data processing instructions
B.22. Floating-point double-precision data processing instructions
B.23. Dual issue
B.23.1. Dual issue rules
B.23.2. Permitted combinations
C. ECC Schemes
C.1. ECC scheme selection guidelines
D. Memory Ordering
D.1. Memory ordering
D.2. Virtual AXI peripheral interface
E. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example Cortex-R5 system
2.1. Processor block diagram
2.2. CPU block diagram
2.3. Power-on Reset
2.4. Power-on reset
2.5. AXI interface clocking
2.6. Standby, wake-up
3.1. Byte-invariant big-endian (BE-8) format
3.2. Little-endian format
3.3. Register organization
3.4. Program status register
3.5. Interrupt entry sequence
4.1. System control and configuration registers
4.2. MPU control and configuration registers
4.3. Cache control and configuration registers
4.4. TCM control and configuration registers
4.5. System performance monitor registers
4.6. System validation registers
4.7. MIDR bit assignments
4.8. CTR bit assignments
4.9. TCMTR bit assignments
4.10. MPUIR bit assignments
4.11. MPIDR bit assignments
4.12. PFR0 bit assignments
4.13. PFR1 bit assignments
4.14. ID_DFR0 bit assignments
4.15. ID_MMFR0 bit assignments
4.16. ID_MMFR1 bit assignments
4.17. ID_MMFR2 bit assignments
4.18. ID_MMFR3 bit assignments
4.19. ID_ISAR0 bit assignments
4.20. ID_ISAR1 bit assignments
4.21. ID_ISAR2 bit assignments
4.22. ID_ISAR3 bit assignments
4.23. ID_ISAR4 bit assignments
4.24. CCSIDR bit assignments
4.25. CLIDR Register bit assignments
4.26. CSSELR bit assignments
4.27. SCTLR bit assignments
4.28. ACTLR bit assignments
4.29. Secondary Auxiliary Control Register bit assignments
4.30. CPACR bit assignments
4.31. DFSR bit assignments
4.32. IFSR bit assignments
4.33. Auxiliary fault status registers bit assignments
4.34. MPU Region Base Address Registers bit assignments
4.35. MPU Region Size and Enable Registers bit assignments
4.36. MPU Region Access Control Register bit assignments
4.37. RGNR bit assignments
4.38. Cache operations
4.39. c7 Set and Way bit assignments
4.40. Invalidate and clean operations bit assignments
4.41. BTCM Region Register bit assignments
4.42. ATCM Region Register bit assignments
4.43. Slave Port Control Register bit assignments
4.44. nVAL IRQ Enable Set Register bit assignments
4.45. nVAL FIQ Enable Set Register bit assignments
4.46. nVAL Reset Enable Set Register bit assignments
4.47. VAL Debug Request Enable Set Register bit assignments
4.48. VAL IRQ Enable Clear Register bit assignments
4.49. nVAL FIQ Enable Clear Register bit assignments
4.50. nVAL Reset Enable Clear Register bit assignments
4.51. VAL Debug Request Enable Clear Register bit assignments
4.52. Cache Size Override Register bit assignments
4.53. Correctable Fault Location Register - cache, bit assignments
4.54. Correctable Fault Location Register - TCM, bit assignments
4.55. Build Options 1 Register bit assignments
4.56. Build Options 2 Register bit assignments
4.57. Pin Options Register bit assignments
4.58. Peripheral Interface Region Register bit assignments
6.1. PMCR Register bit assignments
6.2. PMCNTENSET Register bit assignments
6.3. PMCNTENCLR Register bit assignments
6.4. PMOVSR Register bit assignments
6.5. PMSWINC Register bit assignments
6.6. PMSELR Register bit assignments
6.7. PMXEVTYPERx Register bit assignments
6.8. PMUSERENR Register bit assignments
6.9. PMINTENSET Register bit assignments
6.10. PMINTENCLR Register bit assignments
7.1. Overlapping memory regions
7.2. Overlay for stack protection
7.3. Overlapping subregion of memory
8.1. Memory system block diagram
8.2. Error detection and correction schemes
8.3. Nonsequential read operation performed with one RAM access.
8.4. Sequential read operation performed with one RAM access
11.1. FPU register bank
11.2. FPSID Register bit assignments
11.3. FPSCR Register bit assignments
11.4. FPEXC Register bit assignments
11.5. MVFR0 Register bit assignments
11.6. MVFR1 Register bit assignments
12.1. Typical debug system
12.2. DBGDIDR Register bit assignments
12.3. DBGDRAR Register bit assignments
12.4. DBGDSAR Register bit assignments
12.5. DBGDSCR Register bit assignments
12.6. DBGWFAR Register bit assignments
12.7. DBGVCR Register bit assignments
12.8. DBGDSCCR Register bit assignments
12.9. DBGDRCR Register bit assignments
12.10. DBGBCR Registers bit assignments
12.11. DBGWCR Register bit assignments
12.12. DBGOSLSR Register bit assignments
12.13. DBGAUTHSTATUS Register bit assignments
12.14. DBGPRCR Register bit assignments
12.15. DBGPRSR Register bit assignments
12.16. DBGCLAIMSET Register bit assignments
12.17. DBGCLAIMCLR Register bit assignments
12.18. DBGLSR Register bit assignments
12.19. DBGDEVTYPE Register bit assignments
13.1. DBGITETMIF Register bit assignments
13.2. DBGITMISCOUT Register bit assignments
13.3. DBGITMISCIN Register bit assignments
13.4. DBGITCTRL Register bit assignments

List of Tables

1.1. Configurable options
1.2. Configurable options at reset
2.1. Reset modes
3.1. Register mode identifiers
3.2. GE[3:0] settings
3.3. PSR ode bit values
3.4. Exception entry and exit
3.5. Configuration of exception vector address locations
3.6. Exception vectors
3.7. Jazelle register instruction summary
4.1. System control coprocessor register functions
4.2. Summary of CP15 registers and operations
4.3. MIDR bit assignments
4.4. CTR bit assignments
4.5. TCMTR bit assignments
4.6. MPUIR bit assignments
4.7. MPIDR bit assignments
4.8. PFR0 bit assignments
4.9. PFR1 bit assignments
4.10. ID_DFR0 bit assignments
4.11. ID_MMFR0 bit assignments
4.12. ID_MMFR1 bit assignments
4.13. ID_MMFR2 bit assignments
4.14. ID_MMFR3 bit assignments
4.15. ID_ISAR0 bit assignments
4.16. ID_ISAR1 bit assignments
4.17. ID_ISAR2 bit assignments
4.18. ID_ISAR3 bit assignments
4.19. ID_ISAR4 bit assignments
4.20. CCSIDR bit assignments
4.21. Bit field and register encodings for CCSIDR
4.22. CLIDR Register bit assignments
4.23. CSSELR bit assignments
4.24. SCTLR bit assignments
4.25. ACTLR bit assignments
4.26. Secondary Auxiliary Control Register bit assignments
4.27. CPACR bit assignments
4.28. Fault Status Register encodings
4.29. DFSR bit assignments
4.30. IFSR bit assignments
4.31. ADFSR and AIFSR bit assignments
4.32. SideExt and Side bit encodings
4.33. MPU Region Base Address Registers bit assignments
4.34. Region Size Register bit assignments
4.35. MPU Region Access Control Register bit assignments
4.36. TEX[2:0], C, and B encodings
4.37. Inner and Outer cache policy encoding
4.38. Access data permission bit encoding
4.39. RGNR bit assignments
4.40. c7 Set and Way bit assignments
4.41. Widths of the set field for L1 cache sizes
4.42. Invalidate and clean operations bit assignments
4.43. BTCM Region Register bit assignments
4.44. ATCM Region Register bit assignments
4.45. Slave Port Control Register bit assignments
4.46. nVAL IRQ Enable Set Register bit assignments
4.47. nVAL FIQ Enable Set Register bit assignments
4.48. nVAL Reset Enable Set Register bit assignments
4.49. VAL Debug Request Enable Set Register bit assignments
4.50. VAL IRQ Enable Clear Register bit assignments
4.51. nVAL FIQ Enable Clear Register bit assignments
4.52. nVAL Reset Enable Clear Register bit assignments
4.53. VAL Debug Request Enable Clear Register bit assignments
4.54. Cache Size Override Register bit assignments
4.55. Instruction and data cache size encodings
4.56. Correctable Fault Location Register - cache, bit assignments
4.57. Correctable Fault Location Register - TCM, bit assignments
4.58. Build Options 1 Register bit assignments
4.59. Build Options 2 Register bit assignments
4.60. Pin Options Register bit assignments
4.61. Peripheral Interface Region Register bit assignments
6.1. Event bus interface bit functions
6.2. PMCR Register bit assignments
6.3. PMCNTENSET Register bit assignments
6.4. PMCNTENCLR Register bit assignments
6.5. PMOVSR Register bit assignments
6.6. PMSWINC Register bit assignments
6.7. PMSELR Register bit assignments
6.8. PMXEVTYPERx Register bit functions
6.9. PMUSERENR Register bit assignments
6.10. PMINTENSET Register bit assignments
6.11. PMINTENCLR Register bit assignments
7.1. Default memory map
7.2. Memory attributes summary
8.1. Types of aborts
8.2. Cache parity error behavior
8.3. Cache ECC error behavior
8.4. Tag RAM bit descriptions, with parity
8.5. Tag RAM bit descriptions, with ECC
8.6. Tag RAM bit descriptions, no parity or ECC
8.7. Cache sizes and tag RAM organization
8.8. Organization of a dirty RAM line
8.9. Instruction cache data RAM sizes, no parity or ECC
8.10. Data cache data RAM sizes, no parity or ECC
8.11. Instruction cache data RAM sizes, with parity
8.12. Data cache data RAM sizes, with parity
8.13. Data cache RAM bits, with parity
8.14. Instruction cache data RAM sizes with ECC
8.15. Data cache data RAM sizes with ECC
8.16. Data cache RAM bits, with ECC
8.17. Memory types and associated behavior
9.1. AXI master interface attributes
9.2. ARCACHEMm, AWCACHEMm, ARINNERMm, and AWINNERMm encodings
9.3. Non-cacheable LDRB
9.4. LDRH from Strongly Ordered or Device memory
9.5. LDR or LDM1 from Strongly Ordered or Device memory
9.6. LDM5, Strongly Ordered or Device memory
9.7. STRB to Strongly Ordered or Device memory
9.8. STRH to Strongly Ordered or Device memory
9.9. STR or STM1 to Strongly Ordered or Device memory
9.10. STM7 to Strongly Ordered or Device memory to word 0 or 1
9.11. Linefill behavior on the AXI interface
9.12. Cache line write-back
9.13. LDRH from Non-cacheable Normal memory
9.14. LDR or LDM1 from Non-cacheable Normal memory
9.15. LDM5, Non-cacheable Normal memory or cache disabled
9.16. STRH to Cacheable write-through or Non-cacheable Normal memory
9.17. STR or STM1 to Cacheable write-through or Non-cacheable Normal memory
9.18. AXI transaction splitting, all six words in same cache line
9.19. AXI transaction splitting, data in two cache lines
9.20. Non-cacheable LDR or LDM1 crossing a cache line boundary
9.21. Cacheable write-through or Non-cacheable STRH crossing a cache line boundary
9.22. AXI transactions for Strongly Ordered or Device type memory
9.23. AXI transactions for Non-cacheable Normal or Cacheable write-through memory
9.24. AXI slave interface attributes
9.25. RAM region decode
9.26. TCM chip-select decode
9.27. MSB bit for the different TCM RAM sizes
9.28. RAM-Access space
9.29. TRANSFER/AUX space
9.30. Data RAM AUX format, D_Cache, with ECC
9.31. Data RAM AUX format, D_Cache, with parity
9.32. Data RAM AUX format, D_Cache, with no error correction
9.33. Data RAM AUX format, I-cache, with ECC
9.34. Data RAM AUX format, I-cache, with parity
9.35. Data RAM AUX format, I-cache, with ECC
9.36. Data RAM AUX format, D_Cache, with ECC
9.37. Data RAM AUX format, D_Cache, with parity
9.38. Data RAM AUX format, D_Cache, with ECC
9.39. Tag RAM TRANSFER ECC format
9.40. Tag RAM TRANSFER parity format
9.41. Tag RAM TRANSFER format, without error correction
9.42. Dirty RAM TRANSFER format, with ECC
9.43. Dirty RAM TRANSFER format, without ECC
9.44. AXI peripheral port attributes
9.45. ARCACHEPm and AWCACHEPm encodings
9.46. LDRB transfers
9.47. LDRH transfers
9.48. LDR or LDM transfers
9.49. LDM transfers
9.50. STRB transfers
9.51. STRH transfers
9.52. STR or STM transfers
9.53. STM transfers
9.54. LDRH transfers
9.55. LDR or LDM transfers
9.56. LDM transfers
9.57. STRH transfers
9.58. STR or STM transfers
9.59. LDRB transfers
9.60. LDRH transfers
9.61. LDR or LDM of one register
9.62. LDM that transfers five registers
9.63. STRB transfers
9.64. STRH transfers
9.65. STR of one register
9.66. STM of five registers
9.67. LDRH transfers in Normal memory
9.68. LDR transfers in Normal memory
9.69. STRH transfers in Normal memory
9.70. STR transfers in Normal memory
9.71. ACP slave interface attributes
9.72. ACP master interface attributes
10.1. Power management modes
11.1. Instructions undefined in a single-precision only configuration
11.2. VFP system registers
11.3. Accessing VFP system registers
11.4. FPSID Register bit assignments
11.5. FPSCR Register bit assignments
11.6. FPEXC Register bit assignments
11.7. MVFR0 Register bit assignments
11.8. MVFR1 Register bit assignments
11.9. Default NaN values
11.10. QNaN and SNaN handling
12.1. Access to CP14 debug registers
12.2. CP14 debug registers summary
12.3. Debug memory-mapped registers
12.4. External debug interface access permissions
12.5. Terms used in register descriptions
12.6. DBGDIDR Register bit assignments
12.7. DBGDRAR Register bit assignments
12.8. DBGDSAR Register bit assignments
12.9. DBGDSCR Register bit assignments
12.10. Data Transfer Register bit assignments
12.11. DBGWFAR Register bit assignments
12.12. DBGVCR Register bit assignments
12.13. DBGDSCCR Register bit assignments
12.14. DBGDRCR Register functions
12.15. Breakpoint Value Register bit assignments
12.16. Breakpoint Control Register bit assignments
12.17. Meaning of DBGBVR bits [22:20]
12.18. Watchpoint Value Register bit assignments
12.19. DBGWCR Register bit assignments
12.20. DBGOSLSR Register bit assignments
12.21. DBGAUTHSTATUS Register bit assignments
12.22. DBGPRCR Register bit assignments
12.23. DBGPRSR Register bit assignments
12.24. Management Registers
12.25. Processor Identifier Registers
12.26. DBGCLAIMSET Register bit assignments
12.27. DBGCLAIMCLR Register bit assignments
12.28. DBGLSR Register bit assignments
12.29. DBGDEVTYPE Register bit assignments
12.30. Peripheral Identification Registers
12.31. Fields in the Peripheral Identification Registers
12.32. Peripheral ID Register 0 functions
12.33. Peripheral ID Register 1 functions
12.34. Peripheral ID Register 2 functions
12.35. Peripheral ID Register 3 functions
12.36. Peripheral ID Register 4 functions
12.37. Component Identification Registers
12.38. Processor behavior on debug events
12.39. Values in link register after exceptions
12.40. Read PC value after debug state entry
12.41. Authentication signal restrictions
12.42. Values to write to DBGBCR for a simple breakpoint
12.43. Values to write to DBGWCR for a simple watchpoint
12.44. Example byte address masks for watchpointed objects
13.1. Integration Test Registers summary
13.2. Output signals that can be controlled by the Integration Test Registers
13.3. Input signals that can be read by the Integration Test Registers
13.4. DBGITETMIF Register bit assignments
13.5. DBGITMISCOUT Register bit assignments
13.6. DBGITMISCIN Register bit assignments
13.7. DBGITCTRL Register bit assignments
A.1. Global signals
A.2. Configuration signals
A.3. Peripheral interface size encodings
A.4. Interrupt signals
A.5. AXI master port signals for the L2 interface
A.6. AXI master port error detection signals
A.7. AXI slave port signals for the L2 interface
A.8. AXI slave port error detection signals
A.9. ACP slave port signals
A.10. ACP slave port error detection signals
A.11. ACP master port signals
A.12. ACP master port error detection signals
A.13. AXI peripheral port signals
A.14. AXI peripheral port error detection signals
A.15. AHB peripheral port signals
A.16. AHB peripheral port error detection signals
A.17. ATCM port signals
A.18. B0TCM port signals
A.19. B1TCM port signals
A.20. Redundant CPU signals
A.21. Debug interface signals
A.22. Debug miscellaneous signals
A.23. ETM interface signals
A.24. Test signals
A.25. MBIST signals
A.26. Validation signals
A.27. FPU signals
A.28. Split/Lock signals
A.29. Power mode signal
B.1. Definition of cycle timing terms
B.2. Register interlock examples
B.3. Data Processing Instruction cycle timing behavior if destination is not PC
B.4. Data Processing instruction cycle timing behavior if destination is the PC
B.5. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
B.6. Media data-processing instructions cycle timing behavior
B.7. Sum of absolute differences instruction timing behavior
B.8. Example interlocks
B.9. Example multiply instruction cycle timing behavior
B.10. Branch instruction cycle timing behavior
B.11. Processor state updating instructions cycle timing behavior
B.12. Cycle timing behavior for stores and loads, other than loads to the PC
B.13. Cycle timing behavior for loads to the PC
B.14. <addr_md_1cycle> and <addr_md_3cycle> LDR example instruction explanation
B.15. Load and Store Double instructions cycle timing behavior
B.16. <addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation
B.17. Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC
B.18. Cycle timing behavior of Load Multiples, with PC in the register list (64-bit aligned)
B.19. RFE and SRS instructions cycle timing behavior
B.20. Synchronization instructions cycle timing behavior
B.21. Coprocessor instructions cycle timing behavior
B.22. SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior
B.23. IT and NOP instructions cycle timing behavior
B.24. Floating-point register transfer instructions cycle timing behavior
B.25. Floating-point load/store instructions cycle timing behavior
B.26. Floating-point single-precision data processing instructions cycle timing behavior
B.27. Floating-point double-precision data processing instructions cycle timing behavior
B.28. Permitted instruction combinations
E.1. Issue A
E.2. Differences between issue A and issue B
E.3. Differences between issue B and issue C
E.4. Differences between issue C and issue D

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Product Status

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Revision History
Revision A03 August 2010First release for r0p0
Revision B29 October 2010First release for r1p0
Revision C11 February 2011First release for r1p1
Revision D15 September 2011First release for r1p2
Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460D
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