| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0461A |
| Non-Confidential | |
 PDF version | |
| Home > Signal Descriptions > APB signals |
| |||
| Home > Signal Descriptions > APB signals | |||
The programming interface for the TMC control. Table A.4 shows the APB signals. For more information, see AMBA 3 APB Protocol Specification.
Table A.4. APB signals
Signal | Type | Description |
|---|---|---|
PCLKENDBG | Input | Clock enable for APB. |
PADDRDBG[11:2] | Input | Programming address. Occupies a 4KB region of memory. |
PADDRDBG31 | Input | HIGH for external accesses to bypass the Lock Access mechanism. Wire to PADDRDBG[31] in systems. |
PSELDBG | Input | Indicates this device is currently being accessed. |
PENABLEDBG | Input | Indicates second, and subsequent, cycles of a APB transfer. |
PWRITEDBG | Input | This access is a write transfer. |
PRDATADBG[31:0] | Output | Read data bus. |
PWDATADBG[31:0] | Input | Write data bus. |
PREADYDBG | Output | The ready signal used by the slave to extend an APB transfer. |
PSLVERRDBG | Output | Error response of the APB interface. |
| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0461A |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > APB signals |