CoreSight™ Trace Memory Controller Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the TMC
1.1.1. Configuration options
1.1.2. Operational modes
1.2. Example systems with different configurations
1.2.1. CoreSight ETB and TPIU
1.2.2. ETF and TPIU
1.2.3. ETB only
1.2.4. ETR to SDRAM
1.2.5. ETF, ETR, and TPIU
1.2.6. ETR to alternative interface
1.2.7. Local ETF
1.3. Features of TMC
1.3.1. Configurable parameters
1.3.2. Backward-compatible
1.3.3. Connections to the CTI
1.3.4. Scatter-gather table
1.3.5. Buffer drain over ATB
1.3.6. Synchronization request
1.3.7. AXI master interface
1.3.8. Integration registers
1.3.9. Clock gating
1.4. Product revisions
2. Functional Description
2.1. Functional interfaces
2.1.1. Memory interface
2.1.2. ATB interfaces
2.1.3. CLK, PCLKENDBG, and RESETn
2.1.4. AXI master interface
2.1.5. Event interfaces
2.1.6. APB slave interface
2.1.7. AXI low-power interface
2.1.8. Authentication interface
2.1.9. Test
2.1.10. Synchronisation request interface
2.2. Operation
2.2.1. TMC architectural state machine
2.2.2. Standard usage models for the TMC
2.2.3. Formatter and stop sequence
2.2.4. Trigger, flush and stop events
2.2.5. Scatter-gather
2.3. Drive a streaming interface using TMC
2.3.1. Programming
2.3.2. Integration
2.3.3. Unsupported modes of operation
2.4. Backwards compatibility
2.4.1. ID registers
2.4.2. RRP or RWP base
2.4.3. Restrictions while in stopped state
2.4.4. Starting and stopping trace capture
2.4.5. AcqComp, FtEmpty, and FtStopped
2.4.6. Wider memory interface
2.4.7. RWD Register is WO
2.4.8. Empty bit
2.4.9. TRG Register
3. Programmers Model
3.1. About this programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. RAM Size Register
3.3.2. Status Register
3.3.3. RAM Read Data Register
3.3.4. RAM Read Pointer Register
3.3.5. RAM Write Pointer Register
3.3.6. Trigger Counter Register
3.3.7. Control Register
3.3.8. RAM Write Data Register
3.3.9. Mode Register
3.3.10. Latched Buffer Fill Level
3.3.11. Current Buffer Fill Level
3.3.12. Buffer Level Water Mark
3.3.13. RAM Read Pointer High Register
3.3.14. RAM Write Pointer High Register
3.3.15. AXI Control Register
3.3.16. Data Buffer Address Low Register
3.3.17. Data Buffer Address High Register
3.3.18. Formatter and Flush Status Register
3.3.19. Formatter and Flush Control Register
3.3.20. Periodic Synchronization Counter Register
3.3.21. Integration Test ATB Master Data Register 0
3.3.22. Integration Test ATB Master Interface Control 2 Register
3.3.23. Integration Test ATB Master Control Register 1
3.3.24. Integration Test ATB Master Interface Control 0 Register
3.3.25. Integration Test Miscellaneous Output Register 0
3.3.26. Integration Test Trigger In and Flush In Register
3.3.27. Integration Test ATB Data Register 0
3.3.28. Integration Test ATB Control 2 Register
3.3.29. Integration Test ATB Control 1 Register
3.3.30. Integration Test ATB Control 0 Register
3.3.31. Integration Mode Control Register
3.3.32. Claim Tag Set Register
3.3.33. Claim Tag Clear Register
3.3.34. Lock Access Register
3.3.35. Lock Status Register
3.3.36. Authentication Status Register
3.3.37. Device Configuration Register
3.3.38. Device Type Identifier Register
3.3.39. Peripheral ID4 Register
3.3.40. Peripheral ID5 Register
3.3.41. Peripheral ID6 Register
3.3.42. Peripheral ID7 Register
3.3.43. Peripheral ID0 Register
3.3.44. Peripheral ID1 Register
3.3.45. Peripheral ID2 Register
3.3.46. Peripheral ID3 Register
3.3.47. Component ID0 Register
3.3.48. Component ID1 Register
3.3.49. Component ID2 Register
3.3.50. Component ID3 Register
3.4. Register access dependencies
3.4.1. Writes to TMC registers
3.4.2. Reads from TMC registers
A. Signal Descriptions
A.1. Clocks and resets
A.2. ATB interface signals
A.2.1. ATB master interface signals
A.2.2. ATB slave interface signals
A.3. APB signals
A.4. SRAM signals
A.5. AXI signals
A.6. Authentication signals
A.7. Cross-trigger interface
A.8. Synchronization request interface
A.9. Low-power interface signals
A.10. Test interface signals
B. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ETB configuration
1.2. ETF configuration
1.3. ETR configuration
1.4. CoreSight ETB and TPIU
1.5. ETF and TPIU
1.6. ETB only
1.7. ETR to SDRAM
1.8. ETF, ETR, and TPIU
1.9. ETR to alternative interface
1.10. Local ETF
2.1. Interleaved memory interface operation
2.2. AXI low-power operation
2.3. Test mode clock control
2.4. TMC architectural state machine
2.5. Actions taken on input trigger
2.6. Scatter-gather description
2.7. Integrating the TMC with HSSTP
3.1. RSZ Register bit assignments
3.2. STS Register bit assignments
3.3. RRD Register bit assignments
3.4. RRP Register bit assignments
3.5. RWP Register bit assignments
3.6. TRG Register bit assignments
3.7. CTL Register bit assignments
3.8. RWD Register bit assignments
3.9. MODE Register bit assignments
3.10. LBUFLEVEL Register bit assignments
3.11. CBUFLEVEL Register bit assignments
3.12. BUFWM Register bit assignments
3.13. RRPHI Register bit assignments
3.14. RWPHI Register bit assignments
3.15. AXICTL Register bit assignments
3.16. DBALO Register bit assignments
3.17. DBAHI Register bit assignments
3.18. FFSR Register bit assignments
3.19. FFCR Register bit assignments
3.20. PSCR Register bit assignments
3.21. ITATBMDATA0 Register bit assignments
3.22. ITATBMCTR2 Register bit assignments
3.23. ITATBMCTR1 Register bit assignments
3.24. ITATBMCTR0 Register bit assignments
3.25. ITMISCOP0 Register bit assignments
3.26. ITTRFLIN Register bit assignments
3.27. ITATBDATA0 Register bit assignments
3.28. ITATBCTR2 Register bit assignments
3.29. ITATBCTR1 Register bit assignments
3.30. ITATBCTR0 Register bit assignments
3.31. ITCTRL Register bit assignments
3.32. CLAIMSET Register bit assignments
3.33. CLAIMCLR Register bit assignments
3.34. LAR Register bit assignments
3.35. LSR Register bit assignments
3.36. AUTHSTATUS Register bit assignments
3.37. DEVID Register bit assignments
3.38. DEVTYPE Register bit assignments
3.39. PERIPHID4 Register bit assignments
3.40. PERIPHID5 Register bit assignments
3.41. PERIPHID6 Register bit assignments
3.42. PERIPHID7 Register bit assignments
3.43. PERIPHID0 Register bit assignments
3.44. PERIPHID1 Register bit assignments
3.45. PERIPHID2 Register bit assignments
3.46. PERIPHID3 Register bit assignments
3.47. COMPID0 Register bit assignments
3.48. COMPID1 Register bit assignments
3.49. COMPID2 Register bit assignments
3.50. COMPID3 Register bit assignments

List of Tables

2.1. Memory interface signals
2.2. Event generation
2.3. Page table 0 entries during scatter-gather operation
3.1. TMC register summary
3.2. RSZ Register bit assignments
3.3. STS Register bit assignments
3.4. RRD Register bit assignments
3.5. RRP Register bit assignments
3.6. RWP Register bit assignments
3.7. TRG Register bit assignments
3.8. CTL Register bit assignments
3.9. RWD Register bit assignments
3.10. MODE Register bit assignments
3.11. LBUFLEVEL Register bit assignments
3.12. CBUFLEVEL Register bit assignments
3.13. BUFWM Register bit assignments
3.14. RRPHI Register bit assignments
3.15. RWPHI Register bit assignments
3.16. AXICTL Register bit assignments
3.17. DBALO Register bit assignments
3.18. DBAHI Register bit assignments
3.19. FFSR Register bit assignments
3.20. FFCR Register bit assignments
3.21. PSCR Register bit assignments
3.22. ITATBMDATA0 Register bit assignments
3.23. ITATBMCTR2 Register bit assignments
3.24. ITATBMCTR1 Register bit assignments
3.25. ITATBMCTR0 Register bit assignments
3.26. ITMISCOP0 Register bit assignments
3.27. ITTRFLIN Register bit assignments
3.28. ITATBDATA0 Register bit assignments
3.29. ITATBCTR2 Register bit assignments
3.30. ITATBCTR1 Register bit assignments
3.31. ITATBCTR0 Register bit assignments
3.32. ITCTRL Register bit assignments
3.33. CLAIMSET Register bit assignments
3.34. CLAIMCLR Register bit assignments
3.35. LAR Register bit assignments
3.36. LSR Register bit assignments
3.37. AUTHSTATUS Register bit assignments
3.38. DEVID Register bit assignments
3.39. DEVTYPE Register bit assignments
3.40. PERIPHID4 Register bit assignments
3.41. PERIPHID5 Register bit assignments
3.42. PERIPHID6 Register bit assignments
3.43. PERIPHID7 Register bit assignments
3.44. PERIPHID0 Register bit assignments
3.45. PERIPHID1 Register bit assignments
3.46. PERIPHID2 Register bit assignments
3.47. PERIPHID3 Register bit assignments
3.48. COMPID0 Register bit assignments
3.49. COMPID1 Register bit assignments
3.50. COMPID2 Register bit assignments
3.51. COMPID3 Register bit assignments
3.52. Permitted register writes
3.53. Permitted register reads
A.1. Clock and reset signals
A.2. ATB master interface signals
A.3. ATB slave interface signals
A.4. APB signals
A.5. SRAM signals
A.6. AXI signals
A.7. Authentication signals
A.8. Cross-trigger interface signals
A.9. Synchronization request interface signals
A.10. Low-power interface signals
A.11. Test interface signals
B.1. Issue A

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A22 June 2010First release for r0p0
Copyright © 2010 ARM. All rights reserved.ARM DDI 0461A
Non-Confidential