CoreSight Trace Memory Controller Technical Reference Manual: 3.3.1. RAM Size Register

3.3.1. RAM Size Register

The RSZ Register characteristics are:

Purpose

Defines the size, in 32-bit words, of the local RAM buffer.

ETB, ETF configurations: This value is configurable in the RTL MEM_SIZE parameter, but fixed at synthesis. Supported size is in powers of two only.
ETR configuration: This register is programmable, and selects the size of the memory region to be used for trace storage. If the TMC is programmed for scatter-gather operation, the contents of the RSZ Register are ignored.

The size of the trace buffer must be a multiple of the AXI data width. This can be found by looking at the MEMWIDTH field in the DEVID Register.

The maximum trace buffer size permitted is 4GB. The minimum trace buffer size enabled in Software FIFO mode and Hardware FIFO mode is 512 bytes. The minimum trace buffer size enabled in Circular Buffer mode is one AXI dataword. This is useful when writing to a streaming interface. See Drive a streaming interface using TMC.

The burst length programmed in the AXICTL Register, WrBurstLen, must be compatible with the trace buffer size and the AXI data width so that the total number of bytes of data transferred in a burst is not greater than the trace buffer size. Programming an incompatible burst length results in Unpredictable behavior.

Modifying this register when the TMCReady bit, STS Register, 0x00C is clear, or the TraceCaptEn bit, CTL Register, 0x020 is set, results in Unpredictable behavior.

Configurations

Present in all configuration.

Figure 3.1 shows the RSZ Register bit assignments.

Figure 3.1. RSZ Register bit assignments

Table 3.2 shows the RSZ Register bit assignments.

Table 3.2. RSZ Register bit assignments

Bits	Name	Function
[31]	Reserved	Reserved.
[30:0]	RSZ	Size of the RAM in 32-bit words. For example, for 1KB RAM, this register is `0x00000100`. For 4GB RAM, this register is `0x40000000`.

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