CoreSight Trace Memory Controller Technical Reference Manual: 3.3.35. Lock Status Register

CoreSight Trace Memory Controller Technical Reference Manual

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3.3.35. Lock Status Register

The LSR Register characteristics are:

Purpose: Indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers except the Lock Access Register.
External accesses from a debugger, PADDRDBG31 = 1, are not subject to the Lock registers. This register reads as 0 when read from an external debugger, PADDRDBG31 = 1.
Configurations: Present in all configurations.

Figure 3.35 shows the LSR Register bit assignments.

Figure 3.35. LSR Register bit assignments

Table 3.36 shows the LSR Register bit assignments.

Table 3.36. LSR Register bit assignments

Bits	Name	Function
[31:3]	Reserved	Reserved.
[2]	LOCKTYPE	Indicates whether the Lock Access Register (`0xFB0`) is implemented as 8-bit or 32-bit. `0x0` This component implements a 32-bit Lock Access Register.
[1]	LOCKGRANT	Returns the current status of the lock. This bit reads as zero when read from an external debugger, PADDRDBG31 = 1, because external debugger accesses are not subject to Lock Registers. `0x0` Write access is permitted to this device. `0x1` Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted.
[0]	LOCKEXIST	Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger, PADDRDBG31 = 1, because external debugger accesses are not subject to lock registers. `0x0` No lock control mechanism exists, writes to the Lock Access Register, `0xFB0`, are ignored. `0x1` Lock control mechanism is present.

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