2.4.5. Floating-Point Exception Register

The FPEXC characteristics are:

Purpose

Provides global enable control of the Advanced SIMD and VFP extensions.

Usage constraints

This register is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.5 shows the FPEXC bit assignments.

Figure 2.5. FPEXC bit assignments

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Table 2.8 shows the FPEXC bit assignments.

Table 2.8. FPEXC bit assignments 

BitsNameDescription

[31]

EXThe Cortex-A7 NEON MPE does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.

[30]

EN

NEON MPE enable bit:

0

NEON MPE disabled.

1

NEON MPE enabled.

The EN bit is cleared to 0 at reset.

[29]DEX

Defined synchronous instruction exceptional flag. The Cortex-A7 NEON MPE sets this bit to 1 when generating a synchronous bounce because of an attempt to execute a vector operation. All other Undefined Instruction exceptions clear this bit to zero.

See the ARM Architecture Reference Manual for more information.

[28:0]ReservedRAZ/WI.

Note

The Cortex-A7 NEON MPE hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is non-zero set the FPCSR.DEX bit and result in a synchronous VFP Exception. You can use software to emulate the short vector feature, if required.

You can access the FPEXC Register with the following VMRS and VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register
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