2.4.5. Floating-Point Exception Register

The FPEXC characteristics are:


Provides global enable control of the Advanced SIMD and VFP extensions.

Usage constraints

This register is:


Available in all configurations.


See the register summary in Table 2.2.

Figure 2.5 shows the FPEXC bit assignments.

Figure 2.5. FPEXC bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.8 shows the FPEXC bit assignments.

Table 2.8. FPEXC bit assignments 



EXThe Cortex-A7 NEON MPE does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.



NEON MPE enable bit:


NEON MPE disabled.


NEON MPE enabled.

The EN bit is cleared to 0 at reset.


Defined synchronous instruction exceptional flag. The Cortex-A7 NEON MPE sets this bit to 1 when generating a synchronous bounce because of an attempt to execute a vector operation. All other Undefined Instruction exceptions clear this bit to zero.

See the ARM Architecture Reference Manual for more information.



The Cortex-A7 NEON MPE hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is non-zero set the FPCSR.DEX bit and result in a synchronous VFP Exception. You can use software to emulate the short vector feature, if required.

You can access the FPEXC Register with the following VMRS and VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register
Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0462E