2.4.3. Media and VFP Feature Register 0

The MVFR0 characteristics are:


Together with MVFR1, describes the features that the NEON MPE provides.

Usage constraints

This register is:


Available in all configurations.


See the register summary in Table 2.2.

Figure 2.3 shows the MVFR0 bit assignments.

Figure 2.3. MVFR0 bit assignments

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Table 2.6 shows the MVFR0 bit assignments.

Table 2.6. MVFR0 bit assignments 

[31:28]VFP rounding modes

All rounding modes supported. Value is 0x1.

[27:24]Short vectors

Short vectors not supported. Value is 0x0.

[23:20]Square root

Hardware square root supported. Value is 0x1.


Hardware divide supported. Value is 0x1.

[15:12]VFP exception trapping

Software traps not supported. Value is 0x0.


VFPv4 double-precision supported. Value is 0x2.


VFPv4 single-precision supported. Value is 0x2.

[3:0]A_SIMD registers

Thirty-two 64-bit registers supported. Value is 0x2.

You can access the MVFR0 with the following VMRS instruction:

VMRS <Rd>, MVFR0 ; Read Media and VFP Feature Register 0
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