2.4.2. Floating-Point Status and Control Register

The FPSCR characteristics are:

Purpose

Provides User level control of the NEON MPE.

Usage constraints

This register is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.2 shows the FPSCR bit assignments.

Figure 2.2. FPSCR bit assignments

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Table 2.5 shows the FPSCR bit assignments.

Table 2.5. FPSCR bit assignments

BitsNameDescription
[31] N Set to 1 if a comparison operation produces a less than result.
[30]Z Set to 1 if a comparison operation produces an equal result.
[29] C Set to 1 if a comparison operation produces an equal, greater than, or unordered result.
[28] V Set to 1 if a comparison operation produces an unordered result.
[27] QC

Set to 1 if an Advanced SIMD integer operation has saturated since 0 was last written to this bit.

[26] AHP

Alternative Half-Precision control bit:

0

IEEE half-precision format selected.

1

Alternative half-precision format selected.

[25] DN

Default NaN mode control bit:

0

NaN operands propagate through to the output of a floating-point operation.

1

Any operation involving one or more NaNs returns the Default NaN.

Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.

[24] FZ

Flush-to-zero mode control bit:

0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enabled.

Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.

[23:22]RMode

Rounding Mode control field:

b00

Round to Nearest (RN) mode.

b01

Round towards Plus infinity (RP) mode.

b10

round towards Minus infinity (RM) mode.

b11

round towards Zero (RZ) mode.

Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits.

[21:20] Stride

Stride control used for backwards compatibility with short vector operations.

The Cortex-A7 NEON MPE ignores the value of this field.

See the ARM Architecture Reference Manual.

[19]ReservedUNK/SBZP.
[18:16]Len

Vector length, used for backwards compatibility with short vector operation.

If you set this field to a non-zero value, the VFP data-processing instructions generate exceptions.

See the ARM Architecture Reference Manual.

[15:8]ReservedUNK/SBZP.
[7]IDC

Input Denormal cumulative exception flag.

[6:5]ReservedUNK/SBZP.
[4]IXCInexact cumulative exception flag.
[3]UFCUnderflow cumulative exception flag.
[2]OFCOverflow cumulative exception flag.
[1]DZCDivision by Zero cumulative exception flag.
[0]IOCInvalid Operation cumulative exception flag.

You can access the FPSCR with the following VMRS and VMSR instructions:

VMRS <Rd>, FPSCR ; Read Floating-Point Status and Control Register
VMSR FPSCR, <Rt> ; Write Floating-Point Status and Control Register
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