2.4.5. Floating-Point Exception Register

The FPEXC characteristics are:


Provides global enable control of the VFP extension.

Usage constraints

This register is:

  • Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.

  • Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR, see VFP register access.


Available in all configurations.


See the register summary in Table 2.2.

Figure 2.5 shows the FPEXC bit assignments.

Figure 2.5. FPEXC bit assignments

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Table 2.8 shows the FPEXC bit assignments.

Table 2.8. FPEXC bit assignments 





EXThe Cortex-A7 FPU does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.



Cortex-A7 FPU enable bit:


FPU disabled.


FPU enabled.

The EN bit is cleared to 0 at reset.


Defined synchronous instruction exceptional flag. The Cortex-A7 FPU sets this bit when generating a synchronous bounce because of an attempt to execute a vector operation. All other Undefined Instruction exceptions clear this bit to zero.

See the ARM Architecture Reference Manual for more information.


You can access the FPEXC with the following VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register
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