2.1.2. Enabling VFP support

From reset, the Cortex-A7 FPU is disabled. Any attempt to execute a VFP instruction results in an Undefined Instruction exception being taken. To enable software to access VFP features ensure that:

In addition, software must set the FPEXC.EN bit to 1 to enable most VFP operations. See Floating-Point Exception Register.

When VFP operation is disabled because FPEXC.EN is 0, all VFP instructions are treated as Undefined instructions except for execution of the following in privileged modes:

To use the Cortex-A7 FPU in Secure state only

To use the Cortex-A7 FPU in Secure state only, define the CPACR and Floating-Point Exception (FPEXC) registers to enable the Cortex-A7 FPU:

  1. Set the CPACR for access to CP10 and CP11:

    LDR r0, =(0xF << 20)
    
    MCR p15, 0, r0, c1, c0, 2
    
  2. Set the FPEXC EN bit to enable the Cortex-A7 FPU:

    MOV r3, #0x40000000 
    
    VMSR FPEXC, r3
    

At this point the Cortex-A7 processor can execute VFP instructions.

To use the Cortex-A7 FPU in Secure state and Non-secure state

To use the Cortex-A7 FPU in Secure state and Non-secure state, first define the NSACR and then define the CPACR and FPEXC registers to enable the Cortex-A7 FPU.

  1. Set bits [11:10] of the NSACR for access to CP10 and CP11 from both Secure and Non-secure states:

    MRC p15, 0, r0, c1, c1, 2
    
    ORR r0, r0, #2_11<<10 ; enable fpu
    
    MCR p15, 0, r0, c1, c1, 2
    
  2. Set the CPACR for access to CP10 and CP11:

    LDR r0, =(0xF << 20)
    
    MCR p15, 0, r0, c1, c0, 2
    
  3. Set the FPEXC EN bit to enable the Cortex-A7 FPU:

    MOV r3, #0x40000000 
    
    VMSR FPEXC, r3
    

At this point the Cortex-A7 processor can execute VFP instructions.

Note

Operation is unpredictable if you configure the Coprocessor Access Control Register (CPACR) such that CP10 and CP11 do not have identical access permissions.

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