2.3.1. Processor modes for accessing the Cortex-A7 FPU system registers

Table 2.3 shows the processor modes for accessing the Cortex-A7 FPU system registers.

Table 2.3. Accessing Cortex-A7 FPU system registers

Register Privileged access User access
FPEXC EN=0FPEXC EN=1 FPEXC EN=0 FPEXC EN=1
FPSID Permitted Permitted Not permitted Not permitted
FPSCRNot permittedPermittedNot permittedPermitted
MVFR0, MVFR1Permitted Permitted Not permittedNot permitted
FPEXCPermittedPermitted Not permitted Not permitted

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0463E
Non-ConfidentialID112412