1.1. About the Cortex-A7 FPU

The Cortex-A7 FPU is a VFPv4-D16 implementation of the ARMv7 floating-point architecture. It provides low-cost high performance floating-point computation. The Cortex-A7 FPU supports all addressing modes and operations described in the ARM Architecture Reference Manual.

The Cortex-A7 FPU features are:

The Cortex-A7 FPU hardware supports single and double-precision add, subtract, multiply, divide, multiply and accumulate, fused multiply accumulate, and square root operations as described in the ARM VFPv4 architecture. It provides conversions between 16-bit, 32-bit, and 64-bit floating-point formats and ARM integer word formats, with special operations to perform conversions in round-towards-zero mode for high-level language support.

ARMv7 deprecates the use of VFP vector mode. The Cortex-A7 FPU hardware does not support VFP vector operations. The Cortex-A7 FPU provides high speed VFP operation without support code. However, if an application requires VFP vector operation, then it must use support code. See the ARM Architecture Reference Manual for information on VFP vector operation support.


This manual gives information specific to the Cortex-A7 FPU implementation of the ARM VFPv4 extension. See the ARM Architecture Reference Manual for full instruction set and usage details.

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