2.4.4. Media and VFP Feature Register 1

The MVFR1 characteristics are:

Purpose

Together with MVFR0, describes the features that the Cortex-A7 FPU provides.

Usage constraints

This register is:

  • Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.

  • Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR and FPEXC.EN is set to 1, see VFP register access.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.4 shows the MVFR1 bit assignments.

Figure 2.4. MVFR1 bit assignments

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Table 2.7 shows the MVFR1 bit assignments.

Table 2.7. MVFR1 bit assignments 

BitsNameFunction
[31:28]A_SIMD FMACFused Multiply Accumulate supported. Value is 0x1.
[27:24]VFP HPFP

VFP half-precision operations supported. Value is 0x1.

[23:20]A_SIMD HPFPAdvanced SIMD half-precision operations not supported. Value is 0x0.
[19:16]A_SIMD SPFP

Advanced SIMD single-precision operations not supported. Value is 0x0.

[15:12]A_SIMD integer

Advanced SIMD integer operations not supported. Value is 0x0.

[11:8]A_SIMD load/store

Advanced SIMD load/store instructions not supported. Value is 0x0.

[7:4]D_NaN mode

Propagation of NaN values supported for VFP. Value is 0x1.

[3:0]FtZ mode

Full denormal arithmetic operations supported for VFP. Value is 0x1.


You can access the MVFR1 with the following VMRS instruction:

VMRS <Rd>, MVFR1 ; Read Media and VFP Feature Register 1
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