2.4.3. Media and VFP Feature Register 0

The MVFR0 characteristics are:

Purpose

Together with MVFR1, describes the features that the Cortex-A7 FPU provides.

Usage constraints

This register is:

  • Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.

  • Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR and FPEXC.EN is set to 1, see VFP register access.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.3 shows the MVFR0 bit assignments.

Figure 2.3. MVFR0 bit assignments

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Table 2.6 shows the MVFR0 bit assignments.

Table 2.6. MVFR0 bit assignments 

BitsNameFunction
[31:28]VFP rounding modes

All VFP rounding modes supported. Value is 0x1.

[27:24]Short vectors

VFP short vectors not supported. Value is 0x0.

[23:20]Square root

VFP square root operation supported. Value is 0x1.

[19:16]Divide

VFP divide operation supported. Value is 0x1.

[15:12]VFP exception trapping

VFP exception trapping not supported. Value is 0x0.

[11:8]Double-precision

Double-precision operations supported. Value is 0x2.

[7:4]Single-precision

Single-precision operations supported. Value is 0x2.

[3:0]A_SIMD registers

Sixteen 64-bit registers supported. Value is 0x1.


You can access the MVFR0 with the following VMRS instruction:

VMRS <Rd>, MVFR0 ; Read Media and VFP Feature Register 0
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