4.3.29. MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1

The MAIR0 and MAIR1 characteristics are:

Purpose

To provide the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.

Usage constraints

MAIR0 and MAIR1 are:

  • the Secure copies of the registers give the values for memory accesses from Secure state.

  • the Non-secure copies of the registers give the values for memory accesses from Non-secure modes other than Hyp mode.

Configurations

MAIR0 and MAIR1 are:

  • are Banked

  • have write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

See the register summary in Table 4.11.

Figure 4.25 shows the MAIR0 and MAIR1 bit assignments.

Figure 4.25. MAIR0 and MAIR1 bit assignments

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Table 4.55 shows the MAIR0 and MAIR1 bit assignments.

Table 4.55. MAIR0 and MAIR1 bit assignments

BitsNameDescription
[7:0]Attrm[a]

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

  • AttrIndx[2] selects the appropriate MAIR:

    • setting AttrIndx[2] to 0 selects MAIR0

    • setting AttrIndx[2] to 1 selects MAIR1.

  • AttrIndx[2:0] gives the value of m in Attrm.

[a] Where m is 0-7


Table 4.56 shows the MAIRn.Attrm[7:4] encoding.

Table 4.56. MAIRn.Attrm[7:4] encoding

Attrm[7:4][a][b]Meaning
0000Strongly-ordered or Device memory, see encoding of Attrm[3:0].
00RW, RW not 00

Normal memory, Outer Write-Through Cacheable [c]

0100Normal memory, Outer [d] Non-cacheable[c]
01RW, RW not 00

Normal memory, Outer Write-Back Cacheable [c]

10RWNormal memory, Outer [d] Write-Through Cacheable [c]
11RWNormal memory, Outer [d] Write-Back Cacheable [b][c]

[a] Where m is 0-7.

[b] R defines the Outer Read-Allocate policy, and W defined the Outer Write-Allocate policy, see Table 4.58.

[c] Transient attribute is ignored. See the ARM Architecture reference Manual for more information.

[d] See encoding of Attrm[3:0], shown in Table 4.57, for Inner cacheability policies.


Table 4.57 shows the MAIRn.Attrm[7:4] encoding The encoding of Attrn[3:0] depends on the value of Attrn[7:4], as Table 4.57 shows.

Table 4.57. MAIRn.Attrm[3:0] encoding

Attrm[3:0][a][b]Meaning when Attrm[7:4] is 0b0000Meaning when Attrm[7:4] is not 0b0000
0000Strongly-ordered memoryunpredictable.
00RW, RW not 00unpredictableNormal memory, Inner Write-Through Cacheable[c]
0100Device memoryNormal memory, Inner Non-cacheable[c]
01RW, RW not 00unpredictable

Normal memory, Inner Write-Back Cacheable[c]

10RWunpredictableNormal memory, Inner Write-Through Cacheable[c]
11RWunpredictableNormal memory, Inner Write-Back Cacheable[c]

[a] Where m is 0-7.

[b] R defines the Inner Read-Allocate policy, and W defines the Inner Write-Allocate policy, see Table 4.58.

[c] Transient attribute is ignored. See the ARM Architecture reference Manual for more information.


Table 4.58 shows the encoding of the R and W bits that are used, in some Attrm encodings in Table 4.56 and Table 4.57, to define the read-allocate and write-allocate policies:

Table 4.58. Encoding of R and W bits in some Attrm fields

R or WMeaning
0Do not allocate
1Allocate

To access MAIR0 read or write the CP15 register with:

MRC p15, 0, <Rt>, c10, c2, 0    ; Read Memory Attribute Indirection Register 0
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Memory Attribute Indirection Register 0

To access MAIR1, read or write the CP15 register with:

MRC p15, 0, <Rt>, c10, c2, 1    ; Read Memory Attribute Indirection Register 1
MCR p15, 0, <Rt>, c10, c2, 1    ; Write Memory Attribute Indirection Register 1
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