6.6.2. Instruction cache tag and data encoding

The Cortex-A7 MPCore processor instruction cache is significantly different from the data cache and this is shown in the encodings and data format used in the CP15 operations used to access the tag and data memories. Table 6.5 shows the encoding required to select a given cache line. The set-index range parameter (S) is determined by:

S = log2(Instruction cache size (Byte) / 2*32)) for the 2-way set-associative cache.

Table 6.5. Instruction cache tag and data location encoding

Bit-field of RdDescription
[31]Cache Way
[30:S+5]Unused
[S+4:5]Set index
[4:2]Cache data element offset, Data Register only
[1:0]Unused

Table 6.6 shows the tag and valid bits format for the selected cache line using only Data Register 0.

Table 6.6. Instruction cache tag data format

Bit-field of Data Register 0Description
[31]Unused
[30]Valid
[29]

Cache line instruction set mode:

0

ARM.

1

Thumb.

[28]TrustZone Non-secure state (NS)
[27:0]Tag address

The CP15 Instruction Cache Data Read Operation returns two entries from the cache in Data Register 0 and Data Register 1 corresponding to the 16-bit aligned offset in the cache line:

Data Register 0

Bits[17:0] data from cache offset+ 0b00.

Data Register 1

Bits[17:0] data from cache offset+ 0b10.

In ARM mode these two fields combined always represent a single instruction. In Thumb, they can represent any combination of 16-bit and partial or full 32-bit instructions.

The CP15 Data Cache Data Read Operation returns two entries from the cache in Data Register 0 and Data Register 1 corresponding to the 16-bit aligned offset in the cache line:

Data Register 0

Bits[31:0] data from cache offset+ 0b000.

Data Register 1

Bits[31:0] data from cache offset+ 0b100.

The 64 bits of cache data is returned in Data register 0 and Data register 1.

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