6.6.1. Data cache tag and data encoding

The Cortex-A7 MPCore processor data cache consists of a 4-way set-associative structure. The number of sets in each way depends on the configured size of the cache. The encoding, set in Rd in the appropriate MCR instruction, used to locate the required cache data entry for tag and data memory is shown in Table 6.3. It is very similar for both the tag and data RAM access. Data RAM access includes an additional field to locate the appropriate doubleword in the cache line. The set-index range parameter (S) is determined by:

S = log2(Data cache size / 4).

Table 6.3. Data cache tag and data location encoding

Bit-field of RdDescription
[31:30]Cache way
[S+5:6]Set index
[5:3]Cache doubleword data offset, Data Register only

Data cache reads return 64 bits of data in Data Register 0 and Data Register 1. The tag information, MOESI coherency state, outer attributes, and valid, for the selected cache line is returned using Data Register 0 and Data Register 1 using the format shown in Table 6.4. The Cortex-A7 MPCore processor encodes the 4-bit MOESI coherency state across two fields of Data Register 0 and Data Register 1.

Table 6.4. Data cache tag data format

Data Register 0[31:5]Unused
Data Register 0[4:2]

Outer memory attributes

Data Register 0[1:0]Partial MOESI state, from dirty RAM
Data Register 1[31:30]Partial MOESI state, from tag RAM
Data Register 1[29]TrustZone Non-secure state, NS
Data Register 1[28:0]Tag address [39:11[a]]

[a] Bottom N bits not valid on larger cache sizes, where N is (log2(cache size/8KB)).

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