4.2.31. Implementation defined registers

Table 4.28 shows the 32-bit wide implementation defined registers. These registers provide test features and any required configuration options specific to the Cortex-A7 MPCore processor.

Table 4.28. Memory access registers

NameCRnOp1CRmOp2ResetDescription
L2CTLRc91c020x00000000[a]

L2 Control Register

L2ECTLR30x00000000L2 Extended Control Register
CDBGDR0c153[b]c00UNKData Register 0, see Direct access to internal memory
CDBGDR1   1UNKData Register 1, see Direct access to internal memory
CDBGDR2   2UNKData Register 2, see Direct access to internal memory
CDBGDCT  c20UNKData Cache Tag Read Operation Register, see Direct access to internal memory
CDBGICT    1UNKInstruction Cache Tag Read Operation Register, see Direct access to internal memory
CDBGDCD   c40UNKData Cache Data Read Operation Register, see Direct access to internal memory
CDBGICDc93c41UNKInstruction Cache Data Read Operation Register, see Direct access to internal memory
CDBGTD   2UNKTLB Data Read Operation Register, see Direct access to internal memory
CBAR4c00-[c]Configuration Base Address Register

[a] The reset value depends on the processor configuration.

[b] See Direct access to internal memory for information on how these registers are used.

[c] The reset value depends on the processor configuration.


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