4.3.18. Instruction Set Attribute Register 3

The ID_ISAR3 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR3 is:

  • a read-only register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.16 shows the ID_ISAR3 bit assignments.

Figure 4.16. ID_ISAR3 bit assignments

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Table 4.44 shows the ID_ISAR3 bit assignments.

Table 4.44. ID_ISAR3 bit assignments

BitsNameFunction
[31:28]ThumbEE_extn_instrs

Indicates the supported Thumb Execution Environment (ThumbEE) extension instructions:

0x1

Processor supports ENTERX and LEAVEX instructions, and modifies the load behavior to include null checking.

[27:24]TrueNOP_instrs

Indicates support for True NOP instructions:

0x1

Processor supports true NOP instructions in both the ARM and Thumb instruction sets, and the capability for additional NOP-compatible hints.

[23:20]ThumbCopy_instrs

Indicates the supported Thumb non flag-setting MOV instructions:

0x1

Processor supports Thumb instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register.

[19:16]TabBranch_instrs

Indicates the supported Table Branch instructions in the Thumb instruction set.

0x1

Processor supports TBB and TBH instructions.

[15:12]SynchPrim_instrs

Indicates the supported Synchronization Primitive instructions.

0x2

Processor supports:

  • LDREX and STREX instructions

  • CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions

  • LDREXD and STREXD instructions.

[11:8]SVC_instrs

Indicates the supported SVC instructions:

0x1

Processor supports SVC instruction.

[7:4]SIMD_instrs

Indicates the supported Single Instruction Multiple Data (SIMD) instructions.

0x3

Processor supports:

  • SSAT and USAT instructions, and the Q bit in the PSRs

  • PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and the GE[3:0] bits in the PSRs.

[3:0]Saturate_instrs

Indicates the supported Saturate instructions:

0x1

Processor supports QADD, QDADD, QDSUB, QSUB and the Q bit in the PSRs.


To access the ID_ISAR3, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 3 ; Read Instruction Set Attribute Register 3
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