4.3.24. Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Selects the current CCSIDR, see Cache Size ID Register, by specifying:

  • the required cache level

  • the cache type, either instruction or data cache.

Usage constraints

The CSSELR is:

  • a read/write register

  • Banked for the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.20 shows the CSSELR bit assignments.

Figure 4.20. CSSELR bit assignments

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Table 4.49 shows the CSSELR bit assignments.

Table 4.49. CSSELR bit assignments

BitsNameFunction
[31:4]-

Reserved, UNK/SBZP

[3:1]Level

Cache level of required cache:

0b000

Level 1.

0b001

Level 2.

0b010-0b111

Reserved.

[0]InD

Instruction not Data bit:

0

Data or unified cache.

1

Instruction cache.


To access the CSSELR, read or write the CP15 register with:

MRC p15, 2, <Rt>, c0, c0, 0; Read Cache Size Selection Register
MCR p15, 2, <Rt>, c0, c0, 0; Write Cache Size Selection Register
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