4.3.32. Coprocessor Access Control Register

The CPACR characteristics are:

Purpose

Controls access to coprocessors CP0 to CP13. It also enables software to check for the presence of coprocessors CP0 to CP13.

Usage constraints

The CPACR is:

  • a read/write register

  • Common to the Secure and Non-secure states

  • only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.28 shows the CPACR bit assignments.

Figure 4.28. CPACR bit assignments

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Table 4.61 shows the CPACR bit assignments.

Table 4.61. CPACR bit assignments

BitsNameFunction
[31]ASEDIS

Disable Advanced SIMD Functionality:

0

All Advanced SIMD and VFP instructions execute normally.

1

All Advanced SIMD instructions executed take an Undefined instruction exception.

See the Cortex-A7 MPCore Floating-Point Unit Technical Reference Manual and Cortex-A7 MPCore NEON Media Processing Engine Technical Reference Manual for more information.

If FPU is implemented and Advanced SIMD is not implemented, this bit is RAO/WI.

If FPU and Advanced SIMD are not implemented, this bit is UNK/SBZP.

[30]D32DIS

Disable use of registers D16-D31 of the VFP register file:

0

All instructions accessing D0-D31 execute normally.

1

Any VFP instruction that attempts to access any of registers D16-D31 is undefined.

See the Cortex-A7 MPCore Floating-Point Unit Technical Reference Manual and Cortex-A7 MPCore NEON Media Processing Engine Technical Reference Manual for more information.

If FPU is implemented and Advanced SIMD is implemented, ARM deprecates writing a value that is not zero to this bit.

If FPU is implemented and Advanced SIMD is not implemented, this bit is RAO/WI.

If FPU and Advanced SIMD are not implemented, this bit is UNK/SBZP.

[29:24]-

Reserved, RAZ/WI.

[23:22]cp11

Defines the access rights for coprocessor 11:

0b00

Access denied. Attempted accesses generate an Undefined Instruction exception. This is the reset value.

0b01

Access at PL1 or higher only. Attempted accesses in User mode generate an Undefined Instruction exception.

0b10

Reserved.

0b11

Full access.

If FPU and Advanced SIMD are not implemented, this bit is RAZ/WI.

[21:20]cp10

Defines the access rights for coprocessor 10:

0b00

Access denied. Attempted accesses generate an Undefined Instruction exception. This is the reset value.

0b01

Access at PL1 or higher only. Attempted accesses generate an Undefined Instruction exception

0b10

Reserved.

0b11

Full access.

If FPU and Advanced SIMD are not implemented, this bit is RAZ/WI.

[19:0]-

Reserved, RAZ/WI.


Note

If the values of the cp11 and cp10 fields are not the same, the behavior is unpredictable.

To access the CPACR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 2; Read Coprocessor Access Control Register
MCR p15, 0, <Rt>, c1, c0, 2; Write Coprocessor Access Control Register
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