A.4. Generic Interrupt Controller signals

Table A.3 shows the Generic Interrupt Controller (GIC) signals. All signals which include a 4-bit field, [3:0], encode up to four processors. For these signals, bit[0] represents processor 0, bit[1] represents processor 1, bit[2] represents processor 2, and bit[3] represents processor 3.

Table A.3. GIC signals

SignalDirectionDescription
CFGSDISABLE[a]InputDisables write access to some secure GIC registers.

IRQS[N:0][b]

Input

Interrupt request input lines for the GIC where N can be 31, 63, up to 479 by increments of 32.

nFIQ[3:0]Input

FIQ request. Active-LOW, asynchronous fast interrupt request:

0

Activate fast interrupt.

1

Do not activate fast interrupt.

The processor treats the nFIQ input as level-sensitive. To guarantee that an interrupt is taken, ensure the nFIQ input remains asserted until the processor acknowledges the interrupt.

nIRQ[3:0]Input

IRQ request input lines. Active-LOW, asynchronous interrupt request:

0

Activate interrupt.

1

Do not activate interrupt.

The processor treats the nIRQ input as level-sensitive. To guarantee that an interrupt is taken, ensure the nIRQ input remains asserted until the processor acknowledges the interrupt.

nFIQOUT[3:0][a]Output

Active-LOW output of individual processor nFIQ from the GIC.

For use when processors are powered off and interrupts are handled by the GIC under the control of an external power controller.

nIRQOUT[3:0][a]Output

Active-LOW output of individual processor nIRQ from the GIC.

For use when processors are powered off and interrupts are handled by the GIC under the control of an external power controller.

nVFIQ[3:0]Input

Virtual FIQ request. Active-LOW, asynchronous fast interrupt request:

0

Activate fast interrupt.

1

Do not activate fast interrupt.

The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be asserted until the processor acknowledges the interrupt. If the Cortex-A7 MPCore processor is configured to include the GIC, and the GIC is used, the input pins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include the GIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

See GIC configuration for more information.

nVIRQ[3:0]Input

Virtual IRQ request. Active-LOW, asynchronous interrupt request:

0

Activate interrupt.

1

Do not activate interrupt.

The processor treats the nVIRQ input as level-sensitive. The nVIRQ input must be asserted until the processor acknowledges the interrupt. If the Cortex-A7 MPCore processor is configured to include the GIC, and the GIC is used, the input pins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include the GIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

See GIC configuration for more information.

PERIPHBASE[39:15]Input

Specifies the base address for the GIC registers. This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset.

[a] Not used if a GIC is not present.

[b] N is 0 if there is no GIC present.


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