A.3. Configuration signals

Table A.2 shows the configuration signals. All signals which include a 4-bit field, [3:0], encode up to four processors. For these signals, bit[0] represents processor 0, bit[1] represents processor 1, bit[2] represents processor 2, and bit[3] represents processor 3.

Table A.2. Configuration signals

SignalDirectionDescription
CFGEND[3:0]Input

Endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register (SCTLR):

0

EE bit is LOW.

1

EE bit is HIGH.

This pin is only sampled during reset of the processor.

VINITHI[3:0]Input

Location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (SCTLR):

0

Exception vectors start at address 0x00000000.

1

Exception vectors start at address 0xFFFF0000.

This pin is only sampled during reset of the processor.

CFGTE[3:0]Input

Default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (SCTLR):

0

TE bit is LOW.

1

TE bit is HIGH.

This pin is only sampled during reset of the processor.

CLUSTERID[3:0]Input

Value read in the Cluster ID field, bits [11:8], of the CP15 Multiprocessor Affinity Register (MPDIR).

This pin is only sampled during reset of the processor.

CP15SDISABLE[3:0]Input

Disable write access to some secure CP15 registers.

SMPnAMP[3:0]OutputSignals Symmetric MultiProcessing (SMP) mode or Asymmetric MultiProcessing (AMP) for each processor in the Cortex-A7 MPCore processor.

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