10.4.6. Breakpoint Control Registers

The DBGBCR characteristics are:

Purpose

Holds control information for a breakpoint.

Usage constraints

Used in conjunction with a DBGBVR, see Breakpoint Value Registers. Each DBGBVR is associated with a DBGBCR to form a Breakpoint Register Pair (BRP). DBGBVRn is associated with DBGBCRn to form BRPn.

Configurations

The processor implements 6 BRPs, and is specified by the DBGDIDR.BRPs field, see Debug Identification Register.

Attributes

See the register summary in Table 10.1. The debug logic reset value of a DBGBCR is UNK.

Figure 10.7 shows the DBGBCR bit assignments.

Figure 10.7. DBGBCR bit assignments

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Table 10.8 shows the DBGBCR bit assignments.

Table 10.8. DBGBCR bit assignments

BitsNameFunction
[31:29]-

Reserved.

[28:24]Mask

Address mask. The processor does not support address range masking.

[23:20]BT

Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This includes the meaning of the value held in the associated DBGBVR, indicating whether it is an instruction address or a Context ID.

See the ARM Architecture Reference Manual for the meaning of bits[23:20].

[19:16]LBN

Linked Breakpoint Number. If this BRP is programmed for Linked instruction address match or mismatch then this field must be programmed with the number of the BRP that holds the Context ID to be used in the combined instruction address and Context ID comparison. Otherwise, this field must be programmed to 0b00.

Reading this register returns an Unknown value for this field, and the generation of Breakpoint debug events is unpredictable, if either:

  • this BRP is not programmed for Linked instruction address match or mismatch and this field is not programmed to 0b0000

  • this BRP is programmed for Linked instruction address match or mismatch and the BRP indicated by this field does not support Context ID comparison or is not programmed for Linked Context ID match.

See the ARM Architecture Reference Manual for more information.

[15:14]SSC

Security State Control. This field enables the watchpoint to be conditional on the security state of the processor. This field is used with the Hyp Mode Control (HMC), and Privileged Mode Control (PMC), fields. See the ARM Architecture Reference Manual for possible values of the fields, and the mode and security states that can be tested.

[13]HMC

This field determines whether addresses generated in Hyp mode match for watchpoints. See the ARM Architecture Reference Manual for information on addresses in Hyp mode in which a match occurs.

[12:9]-

Reserved.

[8:5]BAS

Byte Address Select. This field enables match or mismatch comparisons on only certain bytes of the word address held in the DBGBVR. The operation of this field depends also on:

  • the DBGBVR meaning field being programmed for instruction address match or mismatch

  • the Address range mask field being programmed to 0b00000, no mask

  • the instruction set state of the processor, indicated by the CPSR.J and CPSR.T bits.

This field must be programmed to 0b1111 if either:

  • the DBGBVR meaning field, bits[23:20], is programmed for Linked or Unlinked Context ID match

  • the Address range mask field, bits[28:24], is programmed to a value other than 0b00000.

If this is not done, the generation of Breakpoint debug events is unpredictable.

[4:3]-

Reserved.

[2:1]PMC

Privileged Mode Control. This field enables breakpoint matching conditional on the mode of the processor:

This field is used with the SSC and HMC fields. See the ARM Architecture Reference Manual for possible values of the fields, and the mode and security states that can be tested.

Note

Bits[2:1] has no effect for accesses made in Hyp mode.

[0]BE

Breakpoint Enable. Tis bit enables the BRP:

0

BRP disabled.

1

BRP enabled.

A BRP never generates a Breakpoint debug event when it is disabled.

Note

The value of the DBGBCR.E bit is Unknown on reset. A debugger must ensure that DBGBCR.E has a defined value before it programs DBGDSCR[15:14] to enable debug.


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