10.4.1. Debug Identification Register

The DBGDIDR characteristics are:

Purpose

Specifies:

  • which version of the Debug architecture is implemented

  • some features of the debug implementation.

Usage constraints

There are no usage constraints. See Debug Device ID Register 1 and Debug Device ID Register 0 for more information about the debug implementation.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 10.1.

Figure 10.2 shows the DBGDIDR bit assignments.

Figure 10.2. DBGDIDR bit assignments

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Table 10.2 shows the DBGDIDR bit assignments.

Table 10.2. DBGDIDR bit assignments

BitsNameFunction
[31:28]WRPs

Indicates the number of Watchpoint Register Pairs (WRPs) implemented:

0x3

The processor implements 4 WRPs.

[27:24]BRPs

Indicates the number of Breakpoint Register Pairs (BRPs) implemented:

0x5

The processor implements 6 BRPs.

[23:20]CTX_CMPs

Indicates the number of BRPs that can be used for Context ID comparison:

0x1

The processor implements 2 breakpoints with Context ID comparison.

[19:16]Version

Indicates the Debug architecture version:

0x5

The processor implements ARMv7.1 Debug architecture.

[15]DEVID_imp

Indicates if the Debug Device ID Register (DBGDEVID ) is implemented:

1

DBGDEVID is implemented.

[14]nSUHD_imp

Indicates if the Secure User Halting Debug is implemented:

1

Secure User halting debug is not implemented.

[13]PCSR_imp

Indicates if the Program Counter Sampling Register (DBGPCSR) implemented as register 33:

1

DBGPCSR is implemented as register 33.

[12]SE_imp

Security Extensions implemented bit:

1

The processor implements Security Extensions.

[11:8]-

Reserved.

[7:4]Variant

This field indicates the variant number of the processor. This number is incremented on functional changes. The value matches bits [23:20] of the CP15 Main ID Register. See Main ID Register for more information.

[3:0]Revision

This field indicates the revision number of the processor. This number is incremented on bug fixes. The value matches bits [3:0] of the CP15 Main ID Register. See Main ID Register for more information.


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