10.4.2. Program Counter Sampling Register

The DBGPCSR characteristics are:

Purpose

Enables a debugger to sample the Program Counter (PC).

Usage constraints

ARM deprecates reading a PC sample through register 33 when the DBGPCSR is also implemented as register 40.

Configurations

DBGPCSR is implemented as both debug register 33 and 40.

Attributes

See the register summary in Table 10.1.

Figure 10.3 shows the DBGPCSR bit assignments.

Figure 10.3. DBGPCSR bit assignments

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Table 10.3 shows the DBGPCSR bit assignments.

Table 10.3. DBGPCSR bit assignments

BitsNameFunction
[31:2]PCS

Program Counter sample value. The sampled value of bits[31:2] of the PC. The sampled value is either the virtual address of an instruction, or the virtual address of an instruction address plus an offset that depends on the processor instruction set state.

DBGDEVID1.PCSROffset indicates whether an offset is applied to the sampled addresses.

[1:0]IS

Instruction set. When an offset is applied to the sampled address, a profiling tool can use the value of this field to calculate the true instruction address as follows:

  • if IS is b00, ((DBGPCSR[31:2] << 2) - 8) is the address of the sampled ARM instruction

  • if IS is bx1, ((DBGPCSR[31:1] << 1) - 4) is the address of the sampled Thumb or ThumbEE instruction.

b00

The sampled instruction is an ARM instruction.

bx1

The sampled instruction is a Thumb or ThumbEE instruction.

b10

Reserved.

See the ARM Architecture Reference Manual for more information.


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