8.2.2. Interrupt sources

The Cortex-A7 MPCore processor can support up to 480 Shared Peripheral Interrupts (SPIs). All interrupt sources are identified by a unique ID.

The Cortex-A7 MPCore processor has the following interrupt sources:

Software Generated Interrupts

SGIs are generated by writing to the Software Generated Interrupt Register (GICD_SGIR). A maximum of 16 SGIs, ID0-ID15, can be generated for each processor interface. An SGI has edge-triggered properties. The software triggering of the interrupt is equivalent to the edge transition of the interrupt signal on a peripheral input.

Private Peripheral Interrupts

A PPI is an interrupt generated by a peripheral that is specific to a single processor. There are seven PPIs for each processor interface:

Legacy nFIQ signal (PPI0)

When the GIC interrupt bypass is in effect, such as after reset, the external nFIQ signal bypasses the interrupt distributor logic and directly drives the interrupt request to the corresponding processor.

When a processor uses the GIC rather than the external nFIQ signal, by enabling its own processor interface, the nFIQ signal is treated like other interrupt lines and uses ID28. The interrupt is active-LOW level-sensitive.

Secure Physical Timer event (PPI1)

This is the event generated from the Secure Physical Timer and uses ID29. The interrupt is level-sensitive.

Non-secure Physical Timer event (PPI2)

This is the event generated from the Non-secure Physical Timer and uses ID30. The interrupt is level-sensitive.

Legacy nIRQ signal (PPI3)

When the GIC interrupt bypass is in effect, such as after reset, the external nIRQ signal bypasses the interrupt distributor logic and directly drives the interrupt request to the corresponding processor.

When a processor uses the GIC rather than the external nIRQ signal, by enabling its own processor interface, the nIRQ signal is treated like other interrupt lines and uses ID31. The interrupt is active-LOW level-sensitive.

Virtual Timer event (PPI4)

This is the event generated from the Virtual Timer and uses ID27. The interrupt is level-sensitive.

Hypervisor Timer event (PPI5)

This is the event generated from the Physical Timer in Hypervisor mode and uses ID26. The interrupt is level-sensitive.

Virtual Maintenance Interrupt (PPI6)

The Virtualization Extensions support in the ARM Generic Interrupt Controller Architecture Specification permits for a maintenance interrupt to be generated under several conditions. The virtual maintenance interrupt uses ID25. The interrupt is level-sensitive.

Shared Peripheral Interrupts

SPIs are triggered by events generated on associated interrupt input lines. The GIC can support up to 480 SPIs corresponding to the external IRQS signal. The number of SPIs available depends on the implemented configuration of the Cortex-A7 MPCore processor. The permitted values are 0-480, in steps of 32. SPIs start at ID32. The SPIs can be configured to be edge-triggered or active-HIGH level-sensitive.

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