11.3. PMU registers summary

The PMU counters and their associated control registers are accessible from the internal CP15 interface and from the Debug APB interface.

Table 11.1 gives a summary of the Cortex-A7 MPCore PMU registers.

Table 11.1. PMU register summary

Register numberOffsetCRnOp1CRmOp2NameTypeDescription
00x000c90c132PMXEVCNTR0RW

Event Count Register, see the ARM Architecture Reference Manual

10x004c90c132PMXEVCNTR1RW
20x008c90c132PMXEVCNTR2RW
30x00Cc90c132PMXEVCNTR3RW
4-300x010-0x78------Reserved
310x07Cc90c130PMCCNTRRW

Cycle Count Register, see the ARM Architecture Reference Manual

32-2550x080-0x3FC----- Reserved
2560x400c90c131PMXEVTYPER0RW

Event Type Selection Register, see the ARM Architecture Reference Manual

2570x404c90c131PMXEVTYPER1RW
2580x408c90c131PMXEVTYPER2RW
2590x40Cc90c131PMXEVTYPER3RW
258-2860x410-0x478------Reserved
2870x47Cc90c131PMXEVTYPER31RWPerformance Monitors Event TypeSelect Register 31,see the ARM Architecture ReferenceManual
288-7670x480-0xBFC------Reserved
7680xC00c90c121PMCNTENSETRW

Count Enable Set Register, see the ARM Architecture Reference Manual

769-7750xC04-0xC1C------Reserved
7760xC20c90c122PMCNTENCLRRW

Count Enable Clear Register, see the ARM Architecture Reference Manual

777-7830xC24-0xC3C------Reserved
7840xC40c90c141PMINTENSETRW

Interrupt Enable Set Register, see the ARM Architecture Reference Manual

785-7910xC44-0xC5C------Reserved
7920xC60c90c142PMINTENCLRRW

Interrupt Enable Clear Register, see the ARM Architecture Reference Manual

793-7990xC64-0xC7C------Reserved
8000xC80c90c123PMOVSRRW

Overflow Flag Status Register, see the ARM Architecture Reference Manual

801-8070xC84-0xC9C------Reserved
8080xCA0c90c124PMSWINCWO

Software Increment Register, see the ARM Architecture Reference Manual

809-8950xCA4-0xDFC------Reserved
8960xE00----PMCFGRROPerformance Monitor Configuration Register, see the ARM Architecture Reference Manual
8970xE04c90c120PMCRRWPerformance Monitor Control Register
8980xE08c90c140PMUSERENRRW

User Enable Register, see the ARM Architecture Reference Manual

899-9030xE0C-0xE1C------Reserved
9040xE20c90c126PMCEID0ROCommon Event Identification Register 0, see the ARM Architecture Reference Manual
9050xE24c90c127PMCEID1ROCommon Event Identification Register 1, see the ARM Architecture Reference Manual
906-10030xE28-0xFAC------Reserved
10040xFB0----PMLARWO

Lock Access Register, see the ARM Architecture Reference Manual

10050xFB4----PMLSRRO

Lock Status Register, see the ARM Architecture Reference Manual

10060xFB8    PMAUTHSTATUSRO

Authentication Status Register, see the ARM Architecture Reference Manual

1007-10100xFBC-0xFC8------Reserved
10110xFCC----PMDEVTYPERO

Device Type Register, see the ARM Architecture Reference Manual

10120xFD0----PMPID4ROPerformance Monitors Peripheral Identification Registers
10130xFD4----PMPID5RO
10140xFD8----PMPID6RO
10150xFDC----PMPID7RO
10160xFE0----PMPID0RO
10170xFE4----PMPID1RO
10180xFE8----PMPID2RO
10190xFEC----PMPID3RO
10200xFF0----PMCID0ROPerformance Monitors Component Identification Registers
10210xFF4----PMCID1RO
10220xFF8----PMCID2RO
10230xFFC----PMCID3RO

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