11.5. Events

Table 11.5 shows the events that are generated and the numbers that the PMU uses to reference the events. The table also shows the bit position of each event on the event bus. Event reference numbers that are not listed are reserved.

Table 11.5. Performance monitor events

Event IDPMUEVENT bit position Description
0x00-

Software increment. The register is incremented only on writes to the Software Increment Register. See the ARM Architecture Reference Manual.

0x01 [0]

Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache. Includes the speculative linefills in the count.

0x02 [1]

Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB. Includes the speculative requests in the count.

0x03 [2]

Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache. Counts the number of allocations performed in the Data Cache because of a read or a write.

0x04[3]

Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache. This includes speculative reads.

0x05 [4]

Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB. This does not include micro TLB misses because of PLD, PLI, CP15 Cache operation by MVA and CP15 VA to PA operations.

0x06 [5]

Data read architecturally executed. Counts the number of data read instructions accepted by the Load Store Unit. This includes counting the speculative and aborted LDR/LDM, and the reads because of the SWP instructions.

0x07 [6]

Data write architecturally executed. Counts the number of data write instructions accepted by the Load Store Unit. This includes counting the speculative and aborted STR/STM, and the writes because of the SWP instructions.

0x08 [7]Instruction architecturally executed.
0x09 [8]

Exception taken. Counts the number of exceptions architecturally taken.

0x0A [9]

Exception return architecturally executed. The following instructions are reported on this event:

  • LDM {..., pc}^

  • RFE

  • DP S pc

0x0B[10]

Change to ContextID retired. Counts the number of instructions architecturally executed writing into the ContextID Register.

0x0C[11]Software change of PC.
0x0D[12]

Immediate branch architecturally executed (taken or not taken). This includes the branches which are flushed due to a previous load/store which aborts late.

0x0E[13]Procedure return (other than exception returns) architecturally executed.
0x0F[14]Unaligned load-store.
0x10[15]

Branch mispredicted/not predicted. Counts the number of mispredicted or not-predicted branches executed. This includes the branches which are flushed because of a previous load/store which aborts late.

0x11-Cycle counter.
0x12[16]

Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor. This includes the branches which are flushed because of a previous load/store which aborts late.

0x13[17]Data memory access.
0x14[18]Instruction Cache access.
0x15[19]Data cache eviction.
0x16 -Level 2 data cache access
0x17-Level 2 data cache refill
0x18 -Level 2 data cache write-back. Data transfers made as a result of a coherency request from the Level 2 caches to outside of the Level 1 and Level 2 caches are not counted. Write-backs made as a result of CP15 cache maintenance operations are counted.
0x19-Bus accesses. Single transfer bus accesses on either of the ACE read or write channels might increment twice in one cycle if both the read and write channels are active simultaneously.Operations that utilise the bus that do not explicitly transfer data, such as barrier or coherency operations are counted as bus accesses.
0x1D-Bus cycle
0x60-Bus access, read
0x61-Bus access, write
0x86[20]IRQ exception taken.
0x87[21]FIQ exception taken.
0xC0[22]External memory request.
0xC1[23]Non-cacheable external memory request.
0xC2[24]Linefill because of prefetch.
0xC3[25]Prefetch linefill dropped.
0xC4[26]Entering read allocate mode.
0xC5[27]Read allocate mode.
0xC6[28]Reserved.
0xC7-ETM Ext Out[0].
0xC8-ETM Ext Out[1].
0xC9[29]Data Write operation that stalls the pipeline because the store buffer is full.
0xCA- Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local Cortex-A7 cluster, rather than accessing the L2 cache or issuing an external read. It increments on each transaction, rather than on each beat of data.

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