5.8. MMU software accessible registers

The system control coprocessor registers, CP15, in conjunction with page table descriptors stored in memory, control the MMU as shown in Table 5.3.

You can access 32-bit registers with instructions of the form:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

You can access 64-bit registers with instructions of the form:

MRCC p15, 0, <Rt>, <Rt2>, <CRn>
MCRR p15, 0, <R>, <CRn>, <CRm>

CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero.

Table 5.3. CP15 register functions

Register

Cross reference

Context ID RegisterSee the ARM Architecture Reference Manual
Control Register
Data Fault Address Register
Data Fault Status Register
Domain Access Control Register
Hyp Auxiliary DFSR
Hyp Auxiliary IFSR
Hyp Data Fault Address Register
Hyp Instruction Fault Address Register
Hyp Instruction Fault Address Register
Hyp Memory Attribute Indirection Register 0
Hyp Memory Attribute Indirection Register 1
Hyp Translation Control Register
Hyp Translation Table Base Register
Virtualization Translation Control Register
Virtualization Translation Table Base Register
Hyp Syndrome Register
Instruction Fault Address Register
Instruction Fault Status Register
Non-secure Access Control Register
Normal Memory Remap Register
Primary Region Remap Register
TLB operations
TLB Type RegisterSee the ARM Architecture Reference Manual
Translation Table Base Control Register
Translation Table Base Register 0
Translation Table Base Register 1

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