5.5. Memory access sequence

When the processor generates a memory access, the MMU:

  1. Performs a lookup for the requested virtual address, current ASID, current VMID, and security state in the relevant instruction or data micro TLB.

  2. Performs a lookup for the requested virtual address, current ASID, current VMID, and security state in the unified main TLB if there is a miss in the relevant micro TLB.

  3. Performs a hardware translation table walk if there is a miss in the main TLB.

You can configure the MMU to perform hardware translation table walks using either the classic VMSAv7 Short-descriptor translation table format, or the Long-descriptor translation table format specified by the LPAE. This is controlled by programming the Extended Address Enable (EAE) bit in the appropriate Secure or Non-secure Translation Table Base Control Register (TTBR). See the ARM Architecture Reference Manual for information on translation table formats.

Note

Translations in Hyp mode and Stage 2 translations are always performed with the Long-descriptor translation table format as specified by the LPAE.

You can configure the MMU to perform translation table walks in cacheable regions using:

If the encoding of the IRGN bits is Write-Back, an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is Write-Through or Non-cacheable, an access to external memory is performed.

In the case of a main TLB miss, the hardware does a translation table walk if the translation table walk is enabled by the:

If translation table walks are disabled, for example, PD0 or EPD0 is set to 1 for TTBR0, or PD1 or EPD1 is set to 1 for TTBR1, the processor returns a Translation fault. If the TLB finds a matching entry, it uses the information in the entry as follows:

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464D
Non-ConfidentialID052812