7.3.2. ACE transfers

Cortex-A7 does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line starting with the critical word first. A burst does not cross a cache line boundary. The instruction linefill length is:

In a system with L2 cache, Instruction side linefills cause 32-byte fetches if the L2 cache is turned off.

The cache linefill fetch length is always 64-bytes on the data side.

The Cortex-A7 MPCore processor generates only a subset of all possible AXI transactions on the master interface.

For Write-Back Write-Allocate transfers the supported transfers are:

For Non-cacheable transactions:

For Device or Strongly-ordered transactions:

For page table walk transactions INCR 1 32-bit, and 64-bit read transfers.

The following points apply to AXI transactions:

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464D