4.3.28. Primary Region Remap Register

The PRRR characteristics are:

Purpose

Controls the top level mapping of the TEX[0], C, and B memory region attributes.

Usage constraints

The PRRR is:

Configurations

The PRRR:

  • is Banked

  • has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

See the register summary in Table 4.11.

Figure 4.24 shows the PRRR bit assignments.

Figure 4.24. PRRR bit assignments

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Table 4.53 shows the PRRR bit assignments.

Table 4.53. PRRR bit assignments

BitsName Function
[24+n][a]NOSn

Outer Shareable property mapping for memory attributes n, if the region is mapped as Normal Shareable. n is the value of the TEX[0], C and B bits, see Table 4.54. The possible values of each NOSn bit are:

0

Memory region is Outer Shareable.

1

Memory region is Inner Shareable.

See Table 5.2 for more information about this field.

[23:20]-Reserved, UNK/SBZP.
[19]NS1

Mapping of S = 1 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • is mapped as Normal memory

  • has the S bit set to 1.

The possible values of the bit are:

0

Region is not Shareable

1

Region is Shareable.

[18]NS0

Mapping of S = 0 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • is mapped as Normal memory

  • has the S bit set to 0.

The possible values of the bit are the same as those given for the NS1 bit, bit[19].

[17]DS1

Mapping of S = 1 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • is mapped as Device memory

  • has the S bit set to 1.

Note

This field has no significance in the processor.

[16]DS0

Mapping of S = 0 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • is mapped as Device memory

  • has the S bit set to 0.

Note

This field has no significance in the processor.

[2n+1:2n][a]TRn

Primary TEX mapping for memory attributes n. n is the value of the TEX[0], C and B bits, see Table 4.54. This field defines the mapped memory type for a region with attributes n. The possible values of the field are:

0b00

Strongly-ordered.

0b01

Device.

0b10

Normal Memory.

0b11

Reserved, effect is unpredictable.

See Table 5.2 for more information about this field.

[a] Where n is 0-7


Table 4.54 shows the mapping between the memory region attributes and the n value used in the PRRR.nOSn and PRRR.TRn field descriptions.

Table 4.54. Memory attributes and the n value for the PRRR field descriptions

Attributesn value
TEX[0]CB
0000
0011
0102
0113
1004
1015
1106
1117

Large Physical Address Extension, address translations use Long-descriptor translation table formats and MAIR0 replaces the PRRR, and MAIR1 replaces the NMRR. For more information see MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1.

To access the SCTLR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c10, c2, 0    ; Read Primary Region Remap Register
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Primary Region Remap Register
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