2.3.2. Resets

The Cortex-A7 MPCore processor has multiple reset domains with the following reset input signals:

nCOREPORESET[3:0]

These power-on reset signals initialize all the processor logic, including CPU Debug, and breakpoint and watchpoint logic in the processor power domains. They do not reset debug logic in the debug power domain.

nCORERESET[3:0]

These are the primary reset signals which initialize the processor logic in the processor power domains, not including the debug, breakpoint and watchpoint logic.

nDBGRESET[3:0]

At the Cortex-A7 level, these signals reset only the debug, and breakpoint and watchpoint logic in the processor power domain. At the Cortex-A7 integration layer level, these signals also reset the debug logic for each processor, which is in the debug power domain.

These reset signals are 4-bit signals, where each bit represents one processor in the multiprocessor device.

The following reset input signals are single-bit fanouts to all the processors in the multiprocessor device:

nMBISTRESET

This signal resets the device for entry into MBIST mode.

nL2RESET

This signal resets the L2 memory system and the logic in the SCU.

All of these resets:

In Table 2.1, [3:0] specifies the processor configuration and [n] designates the processor that is reset.

Table 2.1. Valid reset combinations

Reset combinationSignalsValueDescription
All processor power-on reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

all = 0

all = 0[a]

all = 0[a]

0

All logic is held in reset.
Individual processor power-on reset with Debug reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

[n] = 0

[n] = 0[a]

[n] = 0[a]

1

Individual processor and Debug are held in reset.
All processor power-on and L2 reset with Debug active

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

all = 0

all = 0

all = 1

0

All processors and L2 are held in reset, so they can be powered up. This enables external debug over power down for all processors.
Individual processor power-on reset with Debug active

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

[n] = 0

[n] = 0

[n] = 1

1

Individual processor is held in reset, so that the processor can be powered up. This enables external debug over power down for the processor that is held in reset.
All processors software reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

all = 1

all = 0

all = 1

1

All logic excluding Debug and L2 memory system is held in reset. All breakpoints and watchpoints are retained.
All processors software reset and L2 reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

all = 1

all = 0

all = 1

0

All logic excluding Debug is held in reset. All breakpoints and watchpoints are retained.
Individual processor software reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

[n] = 1

[n] = 0

[n] = 1

1

Individual processor logic excluding Debug and ETM is held in reset. Breakpoints and watchpoints for that processor are retained.
All processors debug reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

all = 1

all = 1

all = 0

1

Debug is held in reset.
Individual processor Debug reset

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

[n] = 1

[n] = 1

[n] = 0

1

Individual processor Debug is held in reset.
Run mode

nCOREPORESET [3:0]

nCORERESET [3:0]

nDBGRESET [3:0]

nL2RESET

1

1

1

1

No logic is held in reset.

[a] For power-on reset or processor reset, nCOREPORESET must be asserted. The remaining processor resets, nCORERESET and nDBGRESET can be asserted, but is not required.


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