2.4.1. Power domains

The power domains that the Cortex-A7 MPCore processor supports are:

The Cortex-A7 integration layer supports the following power domain:

The separate SCU power domains can remain active even when all the processors are powered down. This enables the Cortex-A7 MPCore processor to accept snoops from an external device to control the L2 cache.

Figure 2.3 shows an example of the domains embedded in a System-on-Chip (SoC) power domain.

Figure 2.3. Power domains

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Figure 2.3 shows the Vdebug power domain for example only. It is a domain in the Cortex-A7 integration layer and is not described in this manual.

Each Vcore<n> domain uses a single clock that is architecturally gated at the top level of the processor to minimize dynamic power consumption without removing power completely from the processor.

At the SoC integration level, the processor logic in Vcore<n> and Vscu can be isolated and powered down completely through the instantiation of clamps on all of the external interfaces inside the Vsoc domain. .

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