4.2.17. 64-bit registers

Table 4.15 gives a summary of the 64-bit wide CP15 system control registers, accessed by the MCRR and MRCC instructions.

Table 4.15. 64-bit register summary

CRnOp1CRmOp2NameResetDescription
-0c2-TTBR0UNKTranslation Table Base Register 0, see the ARM Architecture Reference Manual
-1c2-TTBR1UNKTranslation Table Base Register 1, see the ARM Architecture Reference Manual
-4c2-HTTBRUNK

Hyp Translation Table Base Register, see the ARM Architecture Reference Manual

-6c2-VTTBRUNK[a]

Virtualization Translation Table Base Register, see the ARM Architecture Reference Manual

-0c7-PARUNKPhysical Address Register
-0c14-CNTPCTUNK

Counter Physical Count Register, see the ARM Architecture Reference Manual

-1c14-CNTVCTUNK

Counter Virtual Count Register, see the ARM Architecture Reference Manual

-2c14-CNTP_CVALUNK

Counter PL1 Physical Compare Value Register, see the ARM Architecture Reference Manual

-3c14-CNTV_CVALUNK

Counter PL1 Virtual Compare Value Register, see the ARM Architecture Reference Manual

-4c14-CNTVOFFUNK

Counter Virtual Offset Register, see the ARM Architecture Reference Manual

-6c14-CNTHP_CVALUNK

Counter Non-secure PL2 Physical Compare Value Register, see the ARM Architecture Reference Manual

[a] The reset value for bits [55:48] is 0b00000000.


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