6.5.2. Data prefetching and monitoring

The Cortex-A7 MPCore data cache implements an automatic prefetcher that monitors cache misses in the processor. When a pattern is detected, the automatic prefetcher starts linefills in the background. The prefetcher recognizes a sequence of three data cache misses at a fixed stride pattern that lies in four cache lines, plus or minus. Occasionally these linefills might be dropped before the data is allocated into the cache. Any intervening stores or loads that hit in the data cache do not interfere with the recognition of the cache miss pattern. It can be deactivated in software using a CP15 Auxiliary Control Register bit. See Auxiliary Control Register.

Use the PLD instruction for data prefetching where short sequences or irregular pattern fetches are required.

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