4.3.50. L2 Extended Control Register

The L2ECTLR characteristics are:

Purpose

Provides additional control options for the L2 memory system.

Usage constraints

The L2ECTLR is:

  • a read/write register

  • Common to the Secure and Non-secure states

  • Common to all the processors in the multiprocessor device

  • only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes if NSACR.NS_L2ERR is 0.

    • Read/write in Non-secure PL1 and PL2 modes if NSACR.NS_L2ERR is 1. In this case, all bits are write-ignored except for bit[29].

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.10.

Figure 4.40 shows the L2ECTLR bit assignments.

Figure 4.40. L2ECTLR bit assignments

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Table 4.75 shows the L2ECTLR bit assignments.

Table 4.75. L2ECTLR bit assignments

BitsNameFunction
[31:30]-

Reserved, RAZ/WI.

[29]AXI asynchronous error

AXI asynchronous error indication:

0

No pending AXI asynchronous error. This is the reset value.

1

AXI asynchronous error has occurred.

A write of 0 clears this bit. A write of 1 is ignored.

[28:0]-

Reserved, RAZ/WI.


To access the L2ECTLR, read or write the CP15 register with:

MRC p15, 1, <Rt>, c9, c0, 3; Read L2 Extended Control Register
MCR p15, 1, <Rt>, c9, c0, 3; Write L2 Extended Control Register
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