4.3.47. Hyp Syndrome Register

The HSR characteristics are:

Purpose

Holds syndrome information for an exception taken in Hyp mode.

Usage constraints

The HSR is:

  • a read/write register

  • only accessible from Hyp mode or from Monitor mode when SCR.NS is 1

  • Unknown when executing in Non-secure modes other than Hyp mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.26.

Figure 4.38 shows the HSR bit assignments.

Figure 4.38. HSR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.73 shows the HSR bit assignments.

Table 4.73. HSR bit assignments

BitsNameFunction
[31:26]EC

Exception class. The exception class for the exception that is taken in Hyp mode. See the ARM Architecture Reference Manual for more information.

[25]IL

Instruction length. See the ARM Architecture Reference Manual for more information.

[24:0]ISS

Instruction specific syndrome. See the ARM Architecture Reference Manual for more information. The interpretation of this field depends on the value of the EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00.


Encoding of ISS[24:20] when HSR[31:30] is 0b00

For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20] provides the condition field for the trapped instruction, together with a valid flag for this field. The encoding of this part of the ISS field is:

CV, ISS[24]

Condition valid. Possible values of this bit are:

0

The COND field is not valid.

1

The COND field is valid.

When an instruction is trapped, CV is set to 1.

COND, ISS[23:20]

The Condition field for the trapped instruction. This field is valid only when CV is set to 1.

If CV is set to 0, this field is UNK/SBZP.

When an instruction is trapped, the COND field is 0xE.

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464D
Non-ConfidentialID052812