5.3.3. IPA cache RAM

The IPA cache RAM holds mappings between intermediate physical addresses and physical addresses. Only translations performed in non-secure non-hypervisor modes use this. When a stage 2 translation is completed it is updated, and checked whenever a stage 2 translation is required.

Similarly to the main TLB, it can hold entries for different sizes, and maintains a hitmap of the sizes present so that it does not have to lookup for sizes that are known not to be present.

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