10.6.1. Memory map

The basic memory map supports up to four processors in a multiprocessor device. Table 10.26 shows the address mapping for the debug trace components.

Table 10.26. Address mapping for debug trace components

Address rangeComponent[a]
0x00000 - 0x00FFFROM table
0x01000 - 0x0FFFFReserved
0x10000 - 0x10FFFCPU 0 Debug
0x11000 - 0x11FFFCPU 0 PMU
0x12000 - 0x12FFFCPU 1 Debug
0x13000 - 0x13FFFCPU 1 PMU
0x14000 - 0x14FFFCPU 2 Debug
0x15000 - 0x15FFFCPU 2 PMU
0x16000 - 0x16FFFCPU 3 debug
0x17000 - 0x17FFFCPU 3 PMU
0x18000 - 0x18FFFCPU 0 CTI
0x19000 - 0x19FFFCPU 1 CTI
0x1A000 - 0x1AFFFCPU 2 CTI
0x1B000 - 0x1BFFFCPU 3 CTI
0x1C000 - 0x1CFFFCPU 0 Trace
0x1D000 - 0x1DFFFCPU 1 Trace
0x1E000 - 0x1EFFFCPU 2 Trace
0x1F000 - 0x1FFFFCPU 3 Trace

[a] Indicates the mapped component if present, otherwise reserved.


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