A.6. Power control signals

Table A.5 shows the power control signals. All signals which include a 4-bit field, [3:0], encode up to four processors. For these signals, bit[0] represents processor 0, bit[1] represents processor 1, bit[2] represents processor 2, and bit[3] represents processor 3.

Table A.5. Power control signals

SignalDirectionDescription
EVENTIInputEvent input for processor wake-up from WFE state. See Event communication using WFE or SEV for more information.
EVENTOOutputEvent output. Active when a SEV instruction is executed. See Event communication using WFE or SEV for more information.
STANDBYWFI[3:0]Output

Indicates if a processor is in WFI standby mode:

0

Processor not in WFI standby mode.

1

Processor in WFI standby mode.

STANDBYWFE[3:0]Output

Indicates if a processor is in WFE standby mode:

0

Processor not in WFE standby mode.

1

Processor in WFE standby mode.

STANDBYWFIL2Output

Indicates if the L2 memory system is in WFI standby mode. This signal is active when the following conditions are met:

  • All processors are in standby WFI.

  • ACINACTM is asserted HIGH.

  • L2 memory system is idle.

DBGPWRUPREQ[3:0]Input

Power up request:

0

Power down debug request to the power controller.

1

Power up request to the power controller.

DBGNOPWRDWN[3:0]Output

No power-down request:

0

On a power-down request, the SoC power controller powers down the processor

1

On a power-down request, the SoC power controller does not power down the processor.


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