4.3.8. Processor Feature Register 1

The ID_PFR1 characteristics are:

Purpose

Provides information about the programmers model and architecture extensions supported by the processor.

Usage constraints

The ID_PFR1 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.7 shows the ID_PFR1 bit assignments.

Figure 4.7. ID_PFR1 bit assignments

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Table 4.35 shows the ID_PFR1 bit assignments.

Table 4.35. ID_PFR1 bit assignments

BitsNameFunction
[31:20]-

Reserved, RAZ.

[19:16]Generic Timer

Indicates support for Generic Timer:

0x1

Processor supports Generic Timer.

[15:12]Virtualization Extensions

Indicates support for Virtualization Extensions:

0x1

Processor supports Virtualization Extensions.

[11:8]M profile programmers model

Indicates support for microcontroller programmers model:

0x0

Processor does not support microcontroller programmers model.

[7:4]Security Extensions

Indicates support for Security Extensions. This includes support for Monitor mode and the SMC instruction:

0x1

Processor supports Security Extensions.

[3:0]Programmers model

Indicates support for the standard programmers model for ARMv4 and later.

Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:

0x1

Processor supports the standard programmers model for ARMv4 and later.


To access the ID_PFR1, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 1 ; Read Processor Feature Register 1
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