4.3.35. Hyp System Control Register

The HSCTLR characteristics are:

Purpose

Provides the top level control of the system operation in Hyp mode. In Hype mode this register has access to a subset of SCTLR bits.

Usage constraints

The HSCTLR is:

  • A read/write register.

  • Only accessible from Hyp mode or from Monitor mode when SCR.NS is 1.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.31 shows the HSCTLR bit assignments.

Figure 4.31. HSCTLR bit assignments

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Table 4.64 shows the HSCTLR bit assignments.

Table 4.64. HSCTLR bit assignments

BitsNameFunction
[31]-

Reserved, RAZ/WI.

[30]TE

Thumb Exception enable. This bit controls whether exceptions taken in Hyp mode are taken in ARM or Thumb state:

0

Exceptions taken in ARM state.

1

Exceptions taken in Thumb state.

[29:28]-

Reserved, RAO/WI.

[27:26]-

Reserved, RAZ/WI.

[25]EE

Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector in Hyp mode. This value also indicates the endianness of the translation table data for translation table lookups, when executing in Hyp mode:

0

Little endian.

1

Big endian.

[24]-

Reserved, RAZ/WI.

[23:22]-

Reserved, RAO/WI.

[21]FI

Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency by disabling implementation-defined performance features.

This bit is not implemented, RAZ/WI.

[20]-

Reserved, RAZ/WI.

[19]WXN

Write permission implies Execute Never (XN):

0

Hyp translations that permit write are not forced to be XN.

1

Hyp translations that permit write are forced to be XN.

[18]-

Reserved, RAO/WI.

[17]-

Reserved, RAZ/WI.

[16]-

Reserved, RAO/WI.

[15:13]-

Reserved, RAZ/WI.

[12]I

Instruction cache enable bit for memory accesses made in Hyp mode:

0

Instruction caches disabled.

1

Instruction caches enabled.

[11]-

Reserved, RAO/WI.

[10:7]-

Reserved, RAZ/WI.

[6:3]-

Reserved, RAO/WI.

[2]C

Data and unified cache enable bit for memory accesses made in Hyp mode:

0

Data and unified caches disabled.

1

Data and unified caches enabled.

[1]A

Alignment fault checking enable bit for memory accesses made in Hyp mode:

0

Alignment fault checking disabled.

1

Alignment fault checking enabled.

[0]M

MMU stage 1 address trasnlation enable bit for memory accesses made in Hyp mode:

0

Address translation disabled.

1

Address translation enabled.


To access the HSCTLR, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c0, 0; Read Hyp System Control Register
MCR p15, 4, <Rt>, c1, c0, 0; Write Hyp System Control Register
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