1.5. Configurable options

Table 1.1 shows the Cortex-A7 MPCore RTL configurable options.

Table 1.1. Configurable options for the Cortex-A7 MPCore RTL

FeatureRange of optionsDefault value
Processor-level configuration options:[a]
Floating-Point Unit (FPU) or Media Processing Engine (NEON)Neither, FPU only, FPU and NEON[b]FPU and NEON
Global configuration options:
Instruction cache size 8KB, 16KB, 32KB, or 64KB32KB
Data cache size8KB, 16KB, 32KB, or 64KB32KB
L2 cache controllerPresent or not presentPresent
L2 cache sizesNone, 128KB, 256KB, 512KB, 1024KB256KB
L2 data RAM cycle latency

2 cycles or 3 cycles

2 cycles
Shared Peripheral Interrupts0-480 in steps of 320
Number of processors1, 2, 3, or 42
Integrated GICPresent or not presentNot present

[a] These options can be configured independently for each processor in the Cortex-A7 MPCore processor.

[b] If NEON is selected, FPU is included.


Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464E
Non-ConfidentialID112412