8.3.3. CPU Interface register summary

Each CPU interface provides a programming interface for:

For more information on CPU interfaces, see the ARM Generic Interrupt Controller Architecture Specification.

Table 8.8 shows the register map for the CPU Interface. The offsets in this table are relative to the CPU Interface block base address as shown in Table 8.1.

All the registers in Table 8.8 are word-accessible. Registers not described in this table are RAZ/WI.

Table 8.8. CPU Interface register summary

OffsetNameTypeResetDescription
0x0000

GICC_CTLR

RW0x00000000CPU Interface Control Register, see the ARM Generic Interrupt Controller Architecture Specification
0x0004

GICC_PMRn

RW0x00000000Interrupt Priority Mask Register, see the ARM Generic Interrupt Controller Architecture Specification
0x0008

GICC_BPR

RW

0x00000002 (S)[a]

0x00000003 (NS)[b]

Binary Point Register, see the ARM Generic Interrupt Controller Architecture Specification
0x000C

GICC_IAR

RO0x000003FFInterrupt Acknowledge Register, see the ARM Generic Interrupt Controller Architecture Specification
0x0010

GICC_EOIR

WO-End Of Interrupt Register, see the ARM Generic Interrupt Controller Architecture Specification
0x0014

GICC_RPR

RO0x000000FFRunning Priority Register, see the ARM Generic Interrupt Controller Architecture Specification
0x0018

GICC_HPPIR

RO0x000003FFHighest Priority Pending Interrupt Register, see the ARM Generic Interrupt Controller Architecture Specification
0x001C

GICC_ABPR

RW[c]0x00000003Aliased Binary Point Register, see the ARM Generic Interrupt Controller Architecture Specification

0x0020

GICC_AIAR

RO

0x000003FF

Aliased Interrupt Acknowledge Register

0x0024

GICC_AEOIR

WO

-

Aliased End of Interrupt Register

0x0028

GICC_AHPPIR

RO

0x000003FF

Aliased Highest Priority Pending Interrupt Register

0x00D0-0x00DC

GICC_APR0

RW

0x00000000

Active Priority Register

0x00E0

GICC_NSAPR0

RW[c]0x00000000Non-secure Active Priority Register
0x00FCGICC_IIDRRO0x0102143BCPU Interface Identification Register
0x1000GICC_DIRWO-Deactivate Interrupt Register, see the ARM Generic Interrupt Controller Architecture Specification

[a] (S) = Secure

[b] (NS) = Non-secure

[c] This register is only accessible from a Secure access.


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