A.2. Clock and reset signals

Table A.1 shows the clock, reset and reset control signals. All signals which include a 4-bit field, [3:0], encode up to four processors. For these signals, bit[0] represents processor 0, bit[1] represents processor 1, bit[2] represents processor 2, and bit[3] represents processor 3.

Table A.1. Clock and reset signals

SignalDirectionDescription
CLKINInputGlobal clock.
nCOREPORESET[3:0]Input

All processor reset:

0

Apply reset to all processor logic that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.

1

Do not apply reset to all processor logic that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.

nCORERESET[3:0]Input

Individual processor resets excluding Debug and ETM:

0

Apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.

1

Do not apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.

nDBGRESET[3:0]Input

Debug logic resets:

0

Apply reset to debug, breakpoint and watchpoint logic.

1

Do not apply reset to debug, breakpoint and watchpoint logic.

nL2RESETInput

SCU global reset:

0

Apply reset to shared L2 memory system controller.

1

Do not apply reset to shared L2 memory system controller.

L1RSTDISABLE[3:0]Input

Disable automatic L1 cache invalidate at reset:

0

L1 cache is reset by hardware.

1

L1 cache is not reset by hardware.

L2RSTDISABLEInput

Disable automatic L2 cache invalidate at reset:

0

L2 cache is reset by hardware.

1

L2 cache is not reset by hardware.


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