6.3. L1 instruction memory system

The L1 instruction side memory system is responsible for providing an instruction stream to the Cortex-A7 MPCore processor. To increase overall performance and to reduce power consumption, it contains the following functionality:

The instruction side comprises the following:

Prefetch Unit (PFU)

The PFU implements a 2-level prediction mechanism, comprising the following :

  • A 256-entry branch pattern history table.

  • A 4-entry BTIC.

  • A 8-entry BTAC.

  • A 8-entry return stack.

The prediction scheme is available in ARM state, Thumb state, and ThumbEE state. It is also capable of predicting state changes from ARM to Thumb, and from Thumb to ARM. It does not predict any other state changes, or any instruction that changes the mode of the processor. See Program flow prediction.

Instruction Cache Controller

The instruction cache controller fetches the instructions from memory depending on the program flow predicted by the PFU.

The instruction cache is 2-way set-associative. It comprises the following features:

  • Configurable size of 8KB, 16KB, 32KB, or 64KB.

  • Virtually Indexed Physically Tagged (VIPT).

  • 64-bit native accesses to provide up to four instructions per cycle to the PFU.

  • Security Extensions support.

  • No lockdown support.

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